Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935964
    Abstract: A semiconductor device having high reliability is provided. The semiconductor device includes a transistor and an insulator placed so as to surround the transistor; the insulator has a barrier property against hydrogen; the transistor includes an oxide and a conductor; the conductor includes nitrogen and a metal; the conductor has a physical property of extracting hydrogen; the conductor includes a region having a hydrogen concentration higher than or equal to 2.0×1019 atoms/cm3 and lower than or equal to 1.0×1021 atoms/cm3; and at least part of hydrogen atoms included in the region is bonded to a nitrogen atom.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshihiro Komatsu, Toshikazu Ohno
  • Patent number: 11933974
    Abstract: An object is to provide an electronic device capable of recognizing a user's facial feature accurately. A glasses-type electronic device includes a first optical component, a second optical component, a frame, an imaging device, a feature extraction unit, and an emotion estimation unit. The frame is in contact with a side surface of the first optical component and a side surface of the second optical component. The imaging device is in contact with the frame and has a function of detecting part of a user's face. The feature extraction unit has a function of extracting a feature of the user's face from the detected part of the user's face. The emotion estimation unit has a function of estimating information on the user from the extracted feature.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda, Hidetomo Kobayashi, Hideaki Shishido, Kiyotaka Kimura, Takashi Nakagawa, Kosei Nei, Kentaro Hayashi
  • Patent number: 11936036
    Abstract: A positive electrode active material in which a capacity decrease caused by charge and discharge cycles is suppressed is provided. Alternatively, a positive electrode active material having a crystal structure that is unlikely to be broken by repeated charging and discharging is provided. The positive electrode active material contains titanium, nickel, aluminum, magnesium, and fluorine, and includes a region where titanium is unevenly distributed, a region where nickel is unevenly distributed, and a region where magnesium is unevenly distributed in a projection on its surface. Aluminum is preferably unevenly distributed in a surface portion, not in the projection, of the positive electrode active material.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yohei Momma, Hiroshi Kadoma, Yoshihiro Komatsu, Shiori Saga, Shunpei Yamazaki
  • Publication number: 20240090291
    Abstract: A multifunctional display apparatus with high resolution is provided. The display apparatus includes a first pixel; the first pixel includes a first light-emitting device, a second light-emitting device, and a first light-receiving device; the first light-emitting device includes a first light-emitting layer; the second light-emitting device includes a second light-emitting layer; the second light-emitting device has a function of emitting white light; the first light-emitting device has a function of emitting visible light of a color different from that of the second light-emitting device; the first light-receiving device has a function of sensing light emitted from the first light-emitting device; a side surface of the first light-emitting layer faces a side surface of the second light-emitting layer; and the distance between the side surface of the first light-emitting layer and the side surface of the second light-emitting layer is less than or equal to 8 ?m.
    Type: Application
    Filed: January 19, 2022
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Takayuki IKEDA, Kenichi OKAZAKI, Koji KUSUNOKI
  • Publication number: 20240090302
    Abstract: A high-resolution display apparatus having a function of sensing light is provided. A high-definition display apparatus having a function of sensing light is provided. The display apparatus includes a first light-emitting device, a second light-emitting device, a third light-emitting device, a first light-receiving device, and a second light-receiving device in a first pixel. The first light-emitting device has a function of emitting red light. The second light-emitting device has a function of emitting green light. The third light-emitting device has a function of emitting blue light. The first light-receiving device has a function of sensing light emitted from at least one of the three light-emitting devices. The second light-receiving device has a function of sensing infrared light.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Koji KUSUNOKI, Shingo EGUCHI, Daisuke KUBOTA, Yasuhiro NIIKURA
  • Publication number: 20240087487
    Abstract: A semiconductor device having favorable display quality is provided. The semiconductor device is provided with a display portion, a line-of-sight sensor portion, a control portion, and an arithmetic portion. The line-of-sight sensor portion has a function of obtaining first information showing a direction of a user's line of sight. The arithmetic portion has a function of determining a first region including a gaze point of the user on the display portion with use of the first information and a function of increasing a definition of an image displayed on the first region. Light emitted from the display portion may be used to obtain the first information showing the direction of the line of sight.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Yosuke TSUKAMOTO, Koji KUSUNOKI, Hisao IKEDA, Akio ENDO, Yoshiaki OIKAWA, Hideki UOCHI
  • Publication number: 20240090303
    Abstract: A display device having a function of detecting an object that is in contact with or approaches a display portion is provided. The display device includes a light-emitting element and a light-receiving element. The light-emitting element includes a first pixel electrode, a first functional layer, a light-emitting layer, a common layer, and a common electrode. The light-receiving element includes a second pixel electrode, a second functional layer, a light-receiving layer, the common layer, and the common electrode. The first functional layer includes one of a hole-injection layer and an electron-injection layer. The second functional layer includes one of a hole-transport layer and an electron-transport layer. The common layer has a function of the other of the hole-injection layer and the electron-injection layer in the light-emitting element and has a function of the other of the hole-transport layer and the electron-transport layer in the light-receiving element.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 14, 2024
    Inventors: Daisuke KUBOTA, Ryo HATSUMI, Yasuhiro NIIKURA, Shunpei YAMAZAKI
  • Publication number: 20240090253
    Abstract: A high-resolution display device is provided. A display device having both high display quality and high resolution is provided. The display device includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first pixel electrode, a first EL layer, and a common electrode. The second light-emitting element includes a second pixel electrode, a second EL layer, and the common electrode. An insulating layer containing an inorganic insulating material is provided between the first pixel electrode and the second pixel electrode. The insulating layer includes a first region overlapping with the first EL layer, a second region overlapping with the second EL layer, and a third region positioned between the first region and the second region. A side surface of the first EL layer and a side surface of the second EL layer are positioned over the insulating layer to face each other.
    Type: Application
    Filed: January 14, 2022
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Takayuki IKEDA, Kenichi OKAZAKI, Yasumasa YAMANE
  • Publication number: 20240088172
    Abstract: A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Takashi HAMADA, Kohei YOKOYAMA, Yasuhiro JINBO, Tetsuji ISHITANI, Daisuke KUBOTA
  • Publication number: 20240085944
    Abstract: A display device includes a display panel mounted on a curved surface, and driver circuits including circuit elements which are mounted on a plurality of plane surfaces provided on the back of the curved surface in a stepwise shape along the curved surface.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA
  • Publication number: 20240088162
    Abstract: A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Tomoaki ATSUMI
  • Publication number: 20240090248
    Abstract: A display apparatus having both a personal authentication function and a high resolution is provided. The display apparatus includes a display portion and a sensor portion. The display portion includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first EL layer. The second light-emitting element includes a second EL layer. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light. The light-receiving element has a function of detecting infrared light. A distance between the first EL layer and the second EL layer is less than or equal to 6 ?m.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 14, 2024
    Inventors: Daisuke KUBOTA, Ryo HATSUMI, Shunpei YAMAZAKI
  • Patent number: 11929426
    Abstract: A semiconductor device with high reliability is provided. The present invention relates to a method for manufacturing a transistor including an oxide semiconductor. A stacked-layer structure of an oxide semiconductor and an insulator functioning as a gate insulator is subjected to microwave-excited plasma treatment, whereby the carrier concentration of the oxide semiconductor is reduced and the barrier property of the gate insulator is improved. In addition, a conductor functioning as an electrode and the insulator functioning as a gate insulator are formed in contact with the oxide semiconductor and then the microwave-excited plasma treatment is performed, whereby a high-resistance region and a low-resistance region can be formed in the oxide semiconductor in a self-aligned manner. Moreover, the microwave-excited plasma treatment is performed under an atmosphere containing oxygen with a high pressure, whereby a transistor having favorable electrical characteristics can be provided.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoki Okuno, Hiroki Komagata
  • Patent number: 11929412
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Takahiro Iguchi, Yukinori Shima, Kenichi Okazaki
  • Patent number: 11929416
    Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a first insulator over the second oxide, a first conductor over the first insulator, and a second conductor and a third conductor over the second oxide. The second conductor includes a first region and a second region, the third conductor includes a third region and a fourth region, the second region is positioned above the first region, the fourth region is positioned above the third region, and each of the second conductor and the third conductor contains tantalum and nitrogen. The atomic ratio of nitrogen to tantalum in the first region is higher than the atomic ratio of nitrogen to tantalum in the second region, and the atomic ratio of nitrogen to tantalum in the third region is higher than the atomic ratio of nitrogen to tantalum in the fourth region.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryo Tokumaru, Shinya Sasagawa, Tomonori Nakayama
  • Patent number: 11927862
    Abstract: An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Jun Koyama, Shunpei Yamazaki
  • Patent number: 11929437
    Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Keisuke Murayama
  • Patent number: 11929438
    Abstract: A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region. The first region includes an insulating material and the second region includes a conductive material. The first region and the second region each include a microcrystal whose diameter is greater than or equal to 0.5 nm and less than or equal to 3 nm or a value in the neighborhood thereof. A semiconductor film is formed using the composite target.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20240079502
    Abstract: A semiconductor device with favorable electrical characteristics is to be provided. A highly reliable semiconductor device is to be provided. A semiconductor device with lower power consumption is to be provided. The semiconductor device includes a gate electrode, a first insulating layer over the gate electrode, a metal oxide layer over the first insulating layer, a pair of electrodes over the metal oxide layer, and a second insulating layer over the pair of electrodes. The first insulating layer includes a first region and a second region. The first region has a region being in contact with the metal oxide layer and containing more oxygen than the second region. The second region has a region containing more nitrogen than the first region. The metal oxide layer has at least a concentration gradient of oxygen in a thickness direction, and the concentration gradient becomes high on a first region side and on a second region side.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Junichi KOEZUKA, Kenichi OKAZAKI, Yukinori SHIMA, Yasutaka NAKAZAWA, Yasuharu HOSAKA, Shunpei YAMAZAKI
  • Publication number: 20240079499
    Abstract: To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (In), gallium (Ga), and zinc (Zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed. Further, the composition of the c-axis-aligned crystalline region is represented by In1+?Ga1??O3(ZnO)m (0<?<1 and m=1 to 3 are satisfied), and the composition of the entire oxide semiconductor film including the c-axis-aligned crystalline region is represented by InxGayO3(ZnO)m (0<x<2, 0<y<2, and m=1 to 3 are satisfied).
    Type: Application
    Filed: October 19, 2023
    Publication date: March 7, 2024
    Inventors: Masahiro TAKAHASHI, Kengo AKIMOTO, Shunpei YAMAZAKI