Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942132
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki
  • Patent number: 11943929
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takanori Matsuzaki, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 11940702
    Abstract: A novel composite oxide semiconductor which can be used in a transistor including an oxide semiconductor film is provided. In the composite oxide semiconductor, a first region and a second region are mixed. The first region includes a plurality of first clusters containing In and oxygen as main components. The second region includes a plurality of second clusters containing Zn and oxygen as main components. The plurality of first clusters have portions connected to each other. The plurality of second clusters have portions connected to each other.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11942370
    Abstract: A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoki Okuno, Tetsuya Kakehata, Hiroki Komagata, Yuji Egi
  • Patent number: 11942555
    Abstract: A semiconductor device with favorable electric characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer includes a region in contact with the first insulating layer, the first conductive layer is connected to the oxide semiconductor layer, and the second conductive layer is connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Publication number: 20240095507
    Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 21, 2024
    Inventors: Takahiko ISHIZU, Takayuki IKEDA, Atsuo ISOBE, Atsushi MIYAGUCHI, Shunpei YAMAZAKI
  • Publication number: 20240094574
    Abstract: A touch panel which is thin, has a simple structure, or is easily incorporated into an electronic device is provided. The touch panel includes a first substrate, a second substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, liquid crystal, and an FPC. The first conductive layer has a function of a pixel electrode. The second conductive layer has a function of a common electrode. The third and fourth conductive layers each have a function of an electrode of a touch sensor. The FPC is electrically connected to the fourth conductive layer. The first, second, third, and fourth conductive layers and the liquid crystal are provided between the first and second substrates. The first, second, and third conductive layers are provided over the first substrate. The FPC is provided over the first substrate.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Hajime KIMURA, Shunpei YAMAZAKI
  • Publication number: 20240099054
    Abstract: A highly reliable light-emitting device is provided. Damage to an element due to externally applied physical power is suppressed. Alternatively, in a process of pressure-bonding of an FPC, damage to a resin and a wiring which are in contact with a flexible substrate due to heat is suppressed. A neutral plane at which stress-strain is not generated when a flexible light-emitting device including an organic EL element is deformed, is positioned in the vicinity of a transistor and the organic EL element. Alternatively, the hardness of the outermost surface of a light-emitting device is high. Alternatively, a substrate having a coefficient of thermal expansion of 10 ppm/K or lower is used as a substrate that overlaps with a terminal portion connected to an FPC.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Semiconductor EnergyL aboratoryCo., Ltd.
    Inventors: Shunpei YAMAZAKI, Shingo EGUCHI
  • Publication number: 20240097099
    Abstract: An object of one embodiment of the present invention is to achieve a manufacturing method which can increase capacity density of a secondary battery. Another object is to provide a manufacturing method of a highly safe or reliable secondary battery. The manufacturing method of electrodes (a positive electrode and a negative electrode) of a secondary battery includes a vibration treatment step for supplying vibration to the electrode and a press step for applying pressure to the electrode to compress an active material layer in the electrode. The vibration treatment step is performed before the press step.
    Type: Application
    Filed: January 31, 2022
    Publication date: March 21, 2024
    Inventors: Shunpei YAMAZAKI, Tetsuya KAKEHATA
  • Publication number: 20240096243
    Abstract: A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a display region, a first support, and a second support, the display region includes a first region, a second region, and a third region, the first region and the second region each have a belt-like shape extending in one direction, and the third region is sandwiched between the first region and the second region. The first support overlaps with the first region and is less likely to be warped than the third region, and the second support overlaps with the second region and is less likely to be warped than the third region. The second support can pivot on an axis extending in the one direction with respect to the first support.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Shingo EGUCHI, Taiki NONAKA, Daiki NAKAMURA, Nozomu SUGISAWA, Kazuhiko FUJITA, Shunpei YAMAZAKI
  • Publication number: 20240092655
    Abstract: A novel method for forming a positive electrode active material is provided. In the method for forming a positive electrode active material, a cobalt source and an additive element source are mixed to form an acidic solution; the acidic solution and an alkaline solution are made to react to form a cobalt compound; the cobalt compound and a lithium source are mixed to form a mixture; and the mixture is heated. The additive element source is a compound containing one or more selected from gallium, aluminum, boron, nickel, and indium.
    Type: Application
    Filed: January 21, 2022
    Publication date: March 21, 2024
    Inventors: Shunpei YAMAZAKI, Yusuke YOSHITANI, Yohei MOMMA, Kunihiro FUKUSHIMA, Tetsuya KAKEHATA
  • Publication number: 20240094768
    Abstract: To provide an electronic device capable of a variety of display. To provide an electronic device capable of being operated in a variety of ways. An electronic device includes a display device and first to third surfaces. The first surface includes a region in contact with the second surface, the second surface includes a region in contact with the third surface, and the first surface includes a region opposite to the third surface. The display device includes first to third display regions. The first display region includes a region overlapping with the first surface, the second display region includes a region overlapping with the second surface, and the third display region includes a region overlapping with the third surface. The first display region has a larger area than the third display region.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA
  • Publication number: 20240096242
    Abstract: One embodiment of the present invention provides a display device from which a driver or a fellow passenger in a mobile body such as a vehicle can easily obtain desired information. One embodiment of the present invention is a display device including a display panel. The display panel is placed inside a mobile body including window glass. A film including a light-blocking layer is provided between the window glass and the display panel of the mobile body. By providing a driving unit controlling the display panel, the positional relationship between the window glass and the display panel is changed. Alternatively, by providing a driving unit controlling the film including the light-blocking layer, the positional relationship between the window glass and the film including the light-blocking layer is changed.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 21, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shingo EGUCHI, Hideaki KUWABARA
  • Publication number: 20240099068
    Abstract: A high-resolution display device is provided.
    Type: Application
    Filed: February 8, 2022
    Publication date: March 21, 2024
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Shingo EGUCHI, Ryota HODO
  • Publication number: 20240099070
    Abstract: A high-definition or high-resolution display apparatus is provided. The display apparatus includes a first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, a first light-emitting device, and a second light-emitting device. The top surfaces of the first insulating layer, the first conductive layer, and the second conductive layer are level or substantially level with one another. The first light-emitting device includes a first pixel electrode, a first light-emitting layer, and a common electrode over the first conductive layer. The second light-emitting device includes a second pixel electrode, a second light-emitting layer, and the common electrode over the second conductive layer. The second insulating layer covers a side surface of each of the first pixel electrode, the second pixel electrode, the first light-emitting layer, and the second light-emitting layer.
    Type: Application
    Filed: February 16, 2022
    Publication date: March 21, 2024
    Inventors: Takayuki IKEDA, Kenichi OKAZAKI, Shunpei YAMAZAKI
  • Publication number: 20240094775
    Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yoshiharu HIRAKATA, Hiroyuki MIYAKE, Seiko INOUE, Shunpei YAMAZAKI
  • Patent number: 11934243
    Abstract: To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 11935944
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 11935959
    Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshinari Sasaki, Katsuaki Tochibayashi, Shunpei Yamazaki
  • Patent number: 11935896
    Abstract: Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/?m at room temperature and lower than 100 zA/?m at 85° C.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki