Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11899478
    Abstract: A low-power semiconductor device is provided. A retention transistor is provided between a control circuit and an output transistor. An output terminal of the control circuit is electrically connected to one of a source and a drain of the retention transistor, and the other of the source and the drain of the retention transistor is electrically connected to a gate of the output transistor. A node to which the other of the source and the drain of the retention transistor and the gate of the output transistor are electrically connected is a retention node. When the retention transistor is in an on state, a potential corresponding to a potential output from the control circuit is written to the retention node. Then, when the retention transistor is in an off state, the potential of the retention node is retained. Thus, a gate potential of the output transistor can be kept at a constant value even when the control circuit is off.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keita Sato, Yuto Yakubo, Yoshiaki Oikawa, Shunpei Yamazaki
  • Publication number: 20240047655
    Abstract: A secondary battery has a high capacity and little deterioration can be provided. Alternatively, a novel power storage device is provided. The secondary battery includes a positive electrode and a negative electrode. The negative electrode includes a first active material, a second active material, and a graphene compound. At least part of a surface of the first active material includes a region covered with the second active material. A surface of the second active material and at least part of the surface of the first active material each include a region covered with the graphene compound. The first active material includes graphite. The second active material includes silicon. The capacity of the positive electrode is greater than or equal to 50% and less than 100% of the capacity of the negative electrode.
    Type: Application
    Filed: December 3, 2021
    Publication date: February 8, 2024
    Inventors: Kazutaka KURIKI, Taisuke NAKAO, Teruaki OCHIAI, Tatsuyoshi TAKAHASHI, Shunpei YAMAZAKI
  • Publication number: 20240047468
    Abstract: To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/?m or less and off-state current at 85° C. can be 100 aA/?m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/?m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20240049555
    Abstract: A flexible touch panel is provided. Both reduction in thickness and high sensitivity of a touch panel are achieved. The touch panel includes a first flexible substrate, a first insulating layer over the first substrate, a transistor and a light-emitting element over the first insulating layer, a color filter over the light-emitting element, a pair of sensor electrodes over the color filter, a second insulating layer over the sensor electrodes, a second flexible substrate over the second insulating layer, and a protective layer over the second substrate. A first bonding layer is between the light-emitting element and the color filter. The thickness of the first substrate and the second substrate is each 1 ?m to 200 ?m inclusive. The first bonding layer includes a region with a thickness of 50 nm to 10 ?m inclusive.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 8, 2024
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Hiroyuki MIYAKE
  • Publication number: 20240047751
    Abstract: A lithium-ion secondary battery with high capacity and excellent charge and discharge cycle performance is provided. A secondary battery with high capacity is provided. A secondary battery with excellent charge and discharge characteristics is provided. A secondary battery in which a reduction in capacity is inhibited even when a state being charged with a high voltage is held for a long time is provided. A secondary battery includes a positive electrode, a negative electrode, and an electrolyte, and the amount of moisture in the electrolyte is less than 1000 ppm.
    Type: Application
    Filed: December 2, 2021
    Publication date: February 8, 2024
    Inventors: Kaori OGITA, Fumiko TANAKA, Shotaro MURATSUBAKI, Tetsuji ISHITANI, Shunpei YAMAZAKI
  • Publication number: 20240049449
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: Shunpei YAMAZAKI, Yasuhiko TAKEMURA
  • Publication number: 20240046857
    Abstract: The power consumption of a display device is reduced. The power consumption of a driver circuit in a display device is reduced. A pixel included in the display device includes a display element. The pixel is configured to have a function of retaining a first voltage corresponding to a first input pulse signal and a function of driving the display element with a third voltage obtained by addition of a second voltage corresponding to a second input pulse signal to the first voltage.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Shunpei YAMAZAKI, Kei TAKAHASHI, Susumu KAWASHIMA, Koji KUSUNOKI, Kazunori WATANABE
  • Patent number: 11894380
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11894397
    Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuichi Sato, Hitoshi Nakayama
  • Patent number: 11893299
    Abstract: An electronic device including a housing, a display panel with a flexible substrate, and a flexible printed circuit, in which the housing comprises a flat surface and a side surface comprising a curved region, the display panel comprises a first region that overlaps with the flat surface and a second region that overlaps with the side surface, the display panel comprises a convex portion that comprises a region overlapping with a flexible printed circuit, and the display panel comprises a display portion in the first region and the second region.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 6, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
  • Patent number: 11894486
    Abstract: Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miyuki Hosoba, Suzunosuke Hiraishi
  • Publication number: 20240038899
    Abstract: It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 ?m to 100 ?m inclusive, preferably 3 ?m to 10 ?m inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or ?25° C. to 150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Hiromichi GODO
  • Publication number: 20240038529
    Abstract: A method for depositing a metal oxide is provided. The deposition method of a metal oxide includes a first step of introducing a first precursor into a first chamber, a second step of introducing a second precursor into the first chamber, a third step of introducing a third precursor into the first chamber, a fourth step of introducing an oxidizer in a plasma state into the first chamber after each of the first step, the second step, and the third step, and a fifth step of performing microwave treatment. Performing each of the first to fourth steps one or more times is regarded as one cycle, and the fifth step is performed in a second chamber after the one cycle is repeated a plurality of times.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 1, 2024
    Inventors: Shunpei YAMAZAKI, Yuji EGI, Yasuhiro JINBO, Hitoshi KUNITAKE
  • Publication number: 20240038876
    Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Shunpei YAMAZAKI, Takahiro TSUJI, Kunihiko SUZUKI
  • Patent number: 11887553
    Abstract: A display panel for displaying an image is provided with a plurality of pixels arranged in a matrix. Each pixel includes one or more units each including a plurality of subunits. Each subunit includes a transistor in which an oxide semiconductor layer which is provided so as to overlap a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which drives liquid crystal connected to a source or a drain of the transistor, a counter electrode which is provided so as to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. In the display panel, a transistor whose off current is lower than 10 zA/?m at room temperature per micrometer of the channel width and off current of the transistor at 85° C. can be lower than 100 zA/?m per micrometer in the channel width.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: January 30, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11888073
    Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: January 30, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Publication number: 20240030905
    Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to third transistors and a first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the second transistor, and the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor and a first terminal of the first capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, and the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor and a second terminal of the first capacitor.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 25, 2024
    Inventors: Hajime KIMURA, Shunpei YAMAZAKI
  • Publication number: 20240030429
    Abstract: A positive electrode active material in which the number of defects that cause deterioration is small or progress of the defect is suppressed is provided. The positive electrode active material is used for a secondary battery. The positive electrode active material contains lithium cobalt oxide containing an additive element. After a cycle test is performed on a cell that uses the positive electrode active material for a positive electrode and a lithium electrode as a counter electrode, the positive electrode active material includes a defect and contains at least the same element as the additive element in a region in the vicinity of the defect. The additive element is contained also in a surface portion of the positive electrode active material.
    Type: Application
    Filed: October 28, 2021
    Publication date: January 25, 2024
    Inventors: Shunpei YAMAZAKI, Ryo ARASAWA, Shunichi ITO, Shiori SAGA, Yohei MOMMA, Jo SAITO, Kunihiko SUZUKI, Teppei OGUNI, Yuji IWAKI, Kanta ABE
  • Publication number: 20240026537
    Abstract: A novel method for forming a metal oxide is provided. The metal oxide is formed using a precursor with a high decomposition temperature while a substrate is heated to higher than or equal to 300° C. and lower than or equal to 500° C. In the formation, plasma treatment, microwave treatment, or heat treatment is preferably performed as impurity removal treatment in an atmosphere containing oxygen. The impurity removal treatment may be performed while irradiation with ultraviolet light is performed. The metal oxide is formed by alternate repetition of precursor introduction and oxidizer introduction. For example, the impurity removal treatment is preferably performed every time the precursor introduction is performed more than or equal to 5 times and less than or equal to 10 times.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 25, 2024
    Inventors: Shunpei YAMAZAKI, Tetsuya KAKEHATA, Sachiko KAWAKAMI, Fumito ISAKA, Yuji EGI
  • Publication number: 20240030413
    Abstract: A positive electrode and a secondary battery with little deterioration due to charge and discharge are provided. A positive electrode and a secondary battery with high electrode density are provided. Alternatively, a positive electrode and a secondary battery with excellent rate characteristics are provided. The positive electrode contains a positive electrode active material and a coating material. The coating material covers at least part of a surface of the positive electrode active material, and the positive electrode active material contains lithium cobalt oxide containing magnesium, fluorine, aluminum, and nickel. The lithium cobalt oxide includes a region with the highest concentration of one or more selected from the magnesium, the fluorine, and the aluminum in a surface portion. The coating material is preferably one or more selected from glass, carbon black, graphene, and a graphene compound.
    Type: Application
    Filed: November 29, 2021
    Publication date: January 25, 2024
    Inventors: Shunpei YAMAZAKI, Tetsuya KAKEHATA, Shuhei YOSHITOMI, Atsushi KAWATSUKI