Abstract: The method for forming a DRAM capacitor can include the following steps. First, a first dielectric layer is formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a third dielectric layer on the second dielectric layer. Next, the first, second, and third dielectric layers are patterned to form a contact hole therein. A doped polysilicon layer is then formed within the contact hole and over the third dielectric layer, followed by the formation of a fourth dielectric layer over the doped polysilicon layer. A patterning step patterns the fourth dielectric layer and the doped polysilicon layer to define a storage node. A hemispherical grained silicon layer is then formed on the fourth dielectric layer, on sidewalls of the storage node, and on the third dielectric layer.

Abstract: The method of the present invention is to fabricate a CMOS device without boron penetration. Firstly, a gate oxide layer is formed on a semiconductor substrate. A first silicon layer is formed upon the gate oxide layer. Thereafter, a second silicon layer is stacked on the first silicon substrate, and N type dopant is in situ doped into the second silicon layer, and then a third silicon layer is stacked upon the second silicon layer. A gate structure is formed by patterning the stacked silicon layers, and source/drain structures with LDD regions are subsequently formed in the substrate by ion implantation processes. Finally, a thermal treatment is performed to form shallow source and drain junction in the substrate, thereby achieving the structure of the CMOS device. Meanwhile, the N type dopant is driven to the boundaries of stacked silicon layers of gate structure so as to act as diffusion barriers for suppressing boron penetration.

Abstract: The device includes a gate oxide formed on a semiconductor substrate. Oxide regions are respectively formed on the substrate and adjacent to the gate oxide. Textured oxides are formed on the substrate, between the gate oxide and the oxide regions. A floating gate consists of a first polysilicon portion, second polysilicon portions and a third portion that is composed of hemisperical grained silicon (HSG-Si). The first polysilicon portion is formed on the gate oxide. Isolations are formed on the side walls of the first polysilicon portion. The second polysilicon portions are respectively formed next to the isolations and over a portion of the oxide regions. The HSG-Si is formed on the upper surface of the first polysilicon portion and the second polysilicon portions. A dielectric layer is formed on the HSG-Si of the floating gate. A control gate is formed on the dielectric layer. The doped regions are formed in the substrate and under the textured oxides and the oxide regions.

Abstract: The capacitor includes trenches formed in a semiconductor substrate. Recess portions are formed adjacent to the top portion of the openings of the trenches. An isolation layer is formed on the substrate and on the surface of the recess portions. A first isolation structure is formed on the substrate between the trenches. Second isolation structures are refilled into the recess portions, and the second isolation structures are raised over the isolation layer. A dielectric layer is formed in the trenches along the surface of the trenches. A first storage node is refilled into the trenches. A portion of the first storage node is formed over the first isolation structure to act as a field plate of the capacitor. A third isolation structure is formed on the field plate. The third isolation structure is formed of silicon oxide. A second storage node is formed in the substrate along the surface of the trenches.

Abstract: A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are sequentially formed on a silicon substrate. The nitride cap layer serves as an anti-reflection coating (ARC) layer for improving the resolution of lithography. Then a photo-mask pattern on the ARC layer is formed to define trench regions, an anisotropic etching is performed to etch away unmasked portions of the nitride cap layer through the first polysilicon layer and slightly recess the silicon substrate using the patterned mask as a mask. After removing the patterned mask, a thermal annealed process is performed to grow a polyoxide layer on the sidewall of the first polysilicon layer and an thin oxynitride layer on the surface of the recessed silicon substrate.

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines.

Abstract: The present invention disclosed a structure of a self-aligned crown-shaped rugged capacitor for high density DRAM (dynamic random access memory) cells. The crown-shaped rugged capacitor for high density DRAM cells can be formed without the prior art crack issue. One of the advantages of the structure and a method provided in the invention is that the storage cell can be formed with reduced processing steps. A capacitor cell structure of the present invention includes a first electrode of a first conductive material, a dielectric film, and a second electrode of a second conductive material. The first electrode has a rugged surface on regions uncovered by an underlying dielectric layer, and the first electrode includes a base contact portion, first laterally extended edges, first vertically extended regions, second laterally extended edges, and second vertically extended regions. The dielectric film is formed over the first electrode and the second electrode is formed over the dielectric film.

Abstract: The method includes forming a pad oxide, a polysilicon layer over a substrate. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide layer, the polysilicon layer, and the pad layer. A trench is formed by etching the substrate using the oxide layer as a mask. A sidewall structure is then formed on the opening. Next, an exposed portion of the substrate is etched by using the sidewall structure as a mask. The sidewall structure and the oxide layer are then removed. An oxide and an oxynitride layer are then formed on the aforesaid feature. A semiconductor layer is then formed over the oxynitride layer. A portion of the semiconductor layer is oxidized for forming an insulating layer. Finally, a refilling layer is formed over the insulating layer and the substrate is planarized for having a planar surface.

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as a mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. Trenched isolation regions are formed to isolate and define active regions. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract: A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is etched back, and a metal silicide film is formed and then stripped. A topography of the doped substrate region is then made rugged. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: A MOSFET device with buried contact structure on a semiconductor substrate has the following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of the gate electrode. Inside the substrate, a lightly doped source/drain region is under the gate sidewall structure, and a doped source/drain region is abutting the lightly doped source/drain region and located aside from a region under the gate sidewall structure. In addition, a doped buried contact region is also in the substrate next to the doped source/drain region. On the substrate, a silicon connection is located on a portion of the doped buried contact region, and a shielding block is on the doped buried contact region covering only a region uncovered by the silicon connection.

Abstract: A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is then removed. A polysilicon film is deposited over the substrate 2 and then oxidized into sacrificial oxide layer. After stripping the sacrificial oxide layer, a rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: The present invention provides a mask ROM memory to minimize band-to-band leakage. The substrate includes a normal NMOS device region and a NMOS cell region for coding. An isolation region is formed between the normal NMOS device region and the NMOS cell region. A gate oxide layer is formed on the normal NMOS device region and a coding oxide layer is formed on the NMOS cell region, respectively. In the preferred embodiments, the coding oxide layer has a thickness of about two to ten times that of the gate oxide layer. Main gates are respectively formed on the gate oxide layer and the coding oxide layer. In the present invention, the main gates comprise materials like metal and metal compounds. Spacers are formed on the side walls of the main gates. First doped regions of source and drain regions, or namely lightly doped drains (LDD) and sources, are formed under the spacers and are adjacent to the main gates.

Abstract: The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is then formed over the nitride layer and a first silicon layer is formed over the second oxide layer. Next, a node opening is defined in the first silicon layer, the second oxide layer, and the nitride layer, upon the first oxide layer. Sidewall structures are then formed on sidewalls of the node opening. A contact opening is then defined in the first oxide layer under the node opening. The contact opening is defined in the first oxide layer under a region uncovered by the sidewall structures. The sidewall structures and a portion of the nitride layer nearby the node opening are removed to form undercut structures under the second oxide layer.

Abstract: A structure of a single-electron-transistor memory array is disclosed in the present invention. A substrate is provided. A buried oxide layer is on the substrate. A plurality of silicon wires are arranged on the buried oxide layer, wherein each of the silicon wires has a pair of ends. Oxynitride layers covers on the silicon wires. A polysilicon layer covers the oxynitride layers and the buried oxide layer. A source region and a drain region connect to a first end and a second end of each of the silicon wires, respectively.

Abstract: A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. After the pad oxide film is removed, an undoped silicon film is deposited over the substrate 2 and then etched back by a dry etching. A rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: A method of fabricating high density multiple states mask ROM cells on a semiconductor substrate is disclosed. The method comprises the following steps. Firstly, the array of buried bit line is formed on semiconductor substrate. Then, a CVD oxide film is deposited on said substrate. The first coding mask is applied to dip out the CVD oxide film on the uncoded regions. Then, a thin gate oxide film is thermally grown on said substrate. At the same time, the CVD oxide film is densified and the N+source/drain junction of buried bit lines is formed. A conductive layer is then deposited on all area followed by defining the word lines. The second coding process is performed by using a high energy boron ion implantation through the conductive layer and gate oxide film into said predetermined regions. By combination of the first CVD oxide coding process and the second boron ion implantation coding process, a high density mask ROM with a multiple states is fabricated.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated with a double diffused drain (DDD) junction. In the functional region, a MOSFET structure is characterized as having an anti-punchthrough region beneath the poly-gate, LDD regions beneath sidewall spacers and a silicide layer on the source/drain and the poly-gate. In addition, the n+p junction are ultra shallow. Furthermore, the invention utilizes a liquid phase deposition (LPD) oxide layer to serve as a hard mask for the spacer forming process, salicide process and the S/D implant so as to simplify the fabricating process.

Abstract: A met for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is etched back, and a thin, undoped HSG-Si film is deposited. A wet etching process is performed to etch back by HNO3/CH3COOH/HF/DI, or phosphoric acid (HPO3). The topography of the doped substrate region is then become rugged. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.