Abstract: This invention describes a method to form shallow trench isolation with global planarization. The process steps consist of depositing the etching-resistant masked layers stacked on silicon substrate, where the isolated area region is defined; then the isolated area region is dryly etched and is to be deposited oxidation-resistant thin films and form oxidation-resistant spacers around the side walls of the isolated region with the deposited thin films. Because the thin films and spacers are oxidation resistant, during growth of an oxide film within the isolated area, the bird's beak lateral encroachment can be prevented. This results in nearly abrupt interfaces at the sides of the isolated area. In addition, a high temperature oxidation process is employed to produce a high quality of oxide film and simultaneously recover the possible damages from dry etching.

Abstract: The present invention includes a SOI structure formed in a substrate. A gate is formed over the substrate in a recessed portion of a substrate. A first isolation structure is formed on the side walls of the gate. A second isolation structure is formed adjacent to the first isolation structure. Source and drain regions are formed on the SOI structure. Lightly doped drain (LDD) structures are formed adjacent to the source and drain regions, on the SOI structure and under the second isolation structure. A first metal silicide layer is formed on the source and drain regions and a second metal silicide layer is formed on the gate.

Abstract: A method of fabricating high-density flat cell mask ROM is disclosed. The method comprises, formed a plurality of trenches in a silicon substrate firstly. An oxynitride layer is then grown on resultant surfaces to about 1-5 nm, After refilling a plurality of trenches with a first in-situ phosphorus doping polysilicon layer or amorphous silicon, etching back the polysilicon layer to form a flat surface by a CMP process is achieved. Subsequently, a thermal oxidation process is carried out to grow an oxide layer and to form a plurality of buried bit lines by diffusing the conductive impurities in the polysilicon layer through the oxynitride layer into the silicon substrate. A second in-situ n+ doped polysilicon layer is deposited and patterned as word lines; then a patterned photoresist coated on the second polysilicon layer except predetermining coding regions. Finally, a coding boron implant into the predetermined coding region is done to form normally off transistors.

Abstract: A method for fabricating a capacitor on a semiconductor device is disclosed herein. The method includes the following steps. A first dielectric layer is formed on the semiconductor device in which the semiconductor device has a substrate. Next, a second dielectric layer is formed on the first dielectric layer. Successively, the first dielectric layer, the second dielectric layer and the semiconductor device is etched to form a hole contacting the substrate. Subsequently, a first conductive layer is formed in the hole and on the second dielectric layer. The next step is to pattern the first conductive layer to form a bottom electric electrode of the capacitor. Next, a third dielectric layer is formed on the first conductive layer to make a portion of the first conductive layer that is not covered by the third dielectric layer. The next step is to oxidize the third dielectric layer and the first conductive layer. The silicon dioxide layer is thus formed.

Abstract: A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps: Firstly, a pad oxide layer and a n+ (such as phosphorus) doped oxide layer is successively formed on the silicon substrate. Then, a nitride layer is deposited on all surfaces as an antireflection coating layer. After coating a patterned mask on the nitride layer to define a plurality of buried bit line regions, a dry etch is used to etch the unmask region till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and an oxidation process to grow an oxynitride layer on resultant surface and form buried bit line using dopants in the oxide layer as a diffusion source. After refilling a plurality of trenches with n+ doped silicon layer, a planarization process such as CMP is done to form a plain surface using the nitride layer as an etching stopped layer.

Abstract: The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A second silicon layer is formed over the first dielectric layer. Next, the second silicon layer is patterned to define a gate region. An etching process is performed to the second silicon layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual second silicon layer as a mask. The undoped polysilicon layer is etched by using the residual second silicon layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate.

Abstract: The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited on the substrate and then the tunnel oxide region is defined by a standard photolithography process followed by an anisotropic etching. A high temperature steam oxidation process is used to grow a thick thermal oxide on the non-tunnel region. After removing the masking silicon nitride layer, the n+ impurity ions is implanted to form the source and drain, and a thermal annealing is performed to recover the implantation damage and to drive in the doped ions. Next, the pad oxide film is etched back and an ultra-thin undoped .alpha.-Si, or HSG-Si, film is deposited. A thermal oxidation process is carried out to convert the undoped .alpha.-Si or HSG-Si into textured tunnel oxide.

Abstract: The present invention includes forming word lines on a substrate. Next, nitride spacers are formed on the side walls of the word lines. In the cell area, a photoresist is patterned on the substrate to cover a coding region. Then, an ion implantation with n type conductive dopant is carried out to form buried bit lines in the cell area and in the peripheral area adjacent to the word lines. Afterwards, the photoresist is stripped. A high temperature thermal oxidation is then performed to activate the dopant and to form thick oxide structures to isolate the adjacent buried bit lines.

Abstract: A high-density flat cell mask ROM is disclosed. The mask ROM comprises: a semiconductor substrate having a plurality of trenches and each of the trenches is separated to keep a space with each other. A plurality of oxynitride layers is formed on all sidewall and bottom surfaces of those trenches. A plurality of n+-doped polysilicon layers is formed on the oxynitride layers. A n+ doped silicon layer serves as buried bit line formed in the semiconductor substrate and surrounding the trenches. Each of the doped silicon layers is spaced from the n+-doped polysilicon layers by the oxynitride layer. A plurality of thick oxide layers is formed on the n+ polysilicon layers. A plurality of thin oxide layers are formed on the semiconductor substrate and between those thick oxide layer, and each of thin oxide layers is contiguous with the thick oxide layers.

Abstract: A method of forming contactless array for high density ROM. After floating gates and N.sup.+ buried bit lines are formed, LPD oxide is deposited over the N.sup.+ buried bit lines. Then, a thin oxide layer and a thin nitride layer are successively grown on the floating gates. Moreover, another oxidation process is performed to reoxidize the thin nitride film to become an oxynitride film. Next, a second N.sup.+ polysilicon layer is deposited to form control gates.

Abstract: The transistor structure in the present invention has a recessed region on the top surface of the semiconductor substrate. The transistor has a gate insulator within the recessed region and the gate insulator has a gate space within. A gate electrode is formed within and over the gate space. The transistor has a first insulator layer between the gate electrode and the semiconductor substrate. A semiconductor layer is formed over a portion of the semiconductor substrate uncovered by the gate insulator and the gate electrode. The transistor has a junction region with third type dopants. The junction region is located within the semiconductor substrate under a region uncovered by the gate insulator and the gate electrode. An extended junction region with first type dopants is also created. The extended junction region is located within the semiconductor substrate under the gate insulator. The transistor also has an anti-punchthrough region with second type dopants.

Abstract: A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first doped polysilicon layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A first dielectric layer (119) is formed on the first doped polysiliocn layer, and is then patterned to define a storage node therein. Next, a second doped polysilicon layer (122) is formed on the first dielectric layer and the first doped polysilicon layer, and a second dielectric spacer (124) is formed on a sidewall of the second doped polysilicon layer. After etching the second doped polysilicon layer and the first doped polysilicon layer using the second dielectric spacer as a mask to expose surface of the first dielectric layer, a third doped polysiliocn spacer (126) is formed on a sidewall of the second dielectric spacer.

Abstract: An isolation region is formed in a semiconductor substrate for separating a functional region and a ESD protective region. A gate structure and lightly doped active region is formed. An insulator layer is formed and a portion of the layer is removed for a spacer. A doping is performed using the spacer and gate as a mask. An exposed region located aside the gate is defined in the ESD protective region. A covering layer is formed and a first thermal annealing is performed. A junction diode is also formed. A MOS transistor with self-aligned silicide contacts with an ESD protection improvement is formed. The MOS transistor for the ESD protection in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both kind of transistors in a functional region. The ESD protection effect is raised with a low breakdown junction diode. A lightly doped drain (LDD) structure and an ultra-shallow junction are embedded in the devices.

Abstract: A trench isolation in a semiconductor substrate is provided. The trench isolation includes a recessed region in the semiconductor substrate. The trench isolation also has a first insulator layer lining the recessed region. The first insulator aligns with the semiconductor substrate at edge of the recessed region. The trench isolation further includes a second insulator layer filling within the recessed region over the first insulator. As a preferred embodiment, the recessed region can have well rounded corners at bottom and abutting top surface of the semiconductor substrate. The first insulator has inwardly increased height after the planarization process. The second insulator layer aligns with the first insulator at inner edge of the first insulator. The second insulator layer can also have a top plain region.

Abstract: The method in the present invention is proposed for forming trench isolation in a semiconductor substrate. The method includes the steps as follows. At first, a pad layer is formed over the substrate. A first stacked layer is then formed over the pad layer. Next, a second stacked layer is formed over the first stacked layer. An opening is defined in the second stacked layer, the first stacked layer, and the pad layer. The opening extends down to the substrate. A portion of the substrate is then removed for forming an upper-half portion of a trench by using the second stacked layer as a mask. A sidewall structure is formed on the opening. Next, a portion of the substrate is removed for forming a lower-half portion of the trench by using the sidewall structure as a mask. The sidewall structure and the second stacked layer are removed. Following with the formation of a first insulating layer over the trench, a second insulating layer is formed over the first insulating layer and over the first stacked layer.

Abstract: The present invention discloses a method to simultaneously fabricate the self-aligned silicided devices and ESD protective devices in a substrate. A functional region and a ESD protective region are defined on the substrate and each region has a gate structure. Firstly, lightly doped drain (LDD) regions are formed in both of the region by an ion implantation process. An N-type conducting dopants are implanted into the ESD protective region. Afterwards, the spacers of the gate structures are defined for isolation. A thermal oxidation process is done to grow a thin pad oxide on the functional region and a thicker pad oxide on the ESD protective region. A blanket implantation is performed on all NMOS device. After the implantation process, a RTP process is done to activate the dopants in the substrate and to recover implant damages.

Abstract: The trench capacitors formed in a semiconductor wafer include trenches formed in said semiconductor substrate, first storage nodes includes doped ion regions and doped polysilicon structures, the doped regions are formed in a surface of the trenches. The doped polysilicon structures are formed on the walls of the trenches. An isolation structure is formed on said substrate between said trenches for isolation. A dielectric layer substantially covers the first storage nodes. A field plate is formed on the isolation structure and Second storage nodes is formed in the trenches and on the dielectric layer.

Abstract: The double-stair-like capacitor formed on a semiconductor substrate includes a first storage node having stair-like structures in cross section view to increase the area of the first storage node. A dielectric layer substantially conformally covers a surface of the first storage node. A second storage node having a surface substantially conformally contacts the dielectric layer.

Abstract: A method of making nanometer Si islands for single electron transistors is disclosed. Initially, a pad oxide is deposited over a silicon substrate. Oxygen ions are implanted into the silicon substrate to form an oxygen amorphized region and a high-temperature annealing is performed to form a buried oxide layer in the silicon substrate. Then, a thermal silicon oxide is formed to reduce the thickness of the silicon substrate on the buried oxide layer. The thermal oxide is removed and an ultra-thin oxide layer is then formed on the silicon substrate. A plurality of silicon nitride blocks is formed on the ultra-thin silicon oxide. Afterwards, the spacers of the silicon nitride blocks are formed. The silicon nitride blocks are removed by using wet etching technique. The ultra-thin silicon oxide is etched back and the polysilicon spacers are used as hard mask to Si substrate to form a plurality of nanometer silicon islands.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanocal polishing the layer. A rugged silicon layer is subsequently deposited over the gate and the polished polysilicon. Then, the floating gate is defined. A dielectric is formed at the top of the rugged silicon. A conductive layer is formed on the dielectric layer as a control gate.