Abstract: The method for forming dual threshold circuits on a semiconductor substrate is provided. The semiconductor substrate has a first region, a second region, and a third region. The first region, the second region, and the third region are doped with first type dopants. Then the first region and the second region are doped with second type dopants. The second type dopants are opposite type dopants of the first type dopants. The semiconductor substrate can be performed with more steps to form transistors in the first region, the second region, and the third region.

Abstract: The mask ROM cell structure is described as follows: a plurality of first polysilicon gates is formed on the semiconductor substrate, being separated to keep a space. Each of first polysilicon gates comprises first nitride layer/ a n+ polysilicon layer/a first pad oxide layer, and two spacers that formed over the remnant portion of the pad oxide layer, and formed, respectively, on two sidewalls of the first nitride layer 130, and the first n+ polysilicon layer. A plurality of second polysilicon gates is formed on the semiconductor substrate 105. Each of the second polysilicon gates comprises second n+doped polysilicon gate/second pad oxide layer, wherein the pad oxide layer is formed on the semiconductor substrate, and the n+doped polysilicon gate is formed on the second pad oxide layer. The first polysilicon gates separate the second polysilicon gates each.

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a tilted angle relative to the normal line of the substrate is used. The tilted angle is about 30 to 90 degrees respect to the substrate. The ions pass through the spacers, gate oxide and into the substrate under a portion of the gate by controlling the energy of the ion implantation. The spacers also doped with ions during the implantation. The energy of the ion implantation is about 5 to 150 KeV, and the dosage of the ion implantation is about 5E12 to 2E15 atoms/cm.sup.2. The cap silicon nitride layer is then removed.

Abstract: In the preferred embodiment for forming a rugged polysilicon cup-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed on the first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are then removed to define an opening therein. A second conductive layer is formed conformably on the substrate within the opening and on the first conductive layer. A sidewall structure is then formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer.

Abstract: The present invention includes pad oxides that are separated from each other and on a substrate. First isolations are formed on the pad oxides. Second isolations are formed on the substrate, between the pad oxides. Floating gates are formed on the second isolations and between the first isolations. Third isolations are formed at the top of the floating gates. A word line is formed on the first isolations and on the third isolations. Bit lines are formed in the substrate and under the first isolations.

Abstract: The capacitor of the present invention mainly includes the storage node 52, the capacitor dielectric layer 54, and the conductive layer 56. The storage node 52 is formed on the semiconductor substrate 30, and the storage node 52 includes a base member 52a, two vertical members 52b, two horizontal members 52c, and two sidewall members 52d, in which the base member 52a provides a conductive communication to an underlying conductive region in the substrate 30, the two vertical members 52b respectively extends upward from two lateral ends of the base member 52a, the two horizontal members 52c respectively and outwardly extends from two top ends of the two vertical members 52b, and the two sidewall members 52d respectively and upwardly extending from two outward ends of said two horizontal members 52c. The dielectric layer 54 is covered on the storage node 52 and the conductive layer 56 is formed on the dielectric layer 54.

Abstract: The method of the present invention is a method of including forming a gate oxide layer on the substrate. A polysilicon layer is formed on the gate oxide layer. Then, a photographic and etching steps are used to form a gate structure. An oxidation is performed on the substrate and the gate structure to form an first oxide layer on the substrate and on the surface of the polysilicon gate. A silicon nitride layer is deposited on the first oxide layer. A side-wall spacers is formed on the side walls of the gate structure, a first portion of the first oxide layer remaining between the gate structure and the side-wall spacers, and a second portion of the first oxide layer remaining under the side-wall spacers. Next, a first ion implantation performed into the substrate to form first doped ions regions to serves as source and drain region of the transistor. Then, the side-wall spacers is removed, therefore remained the second portion of the first oxide layer covered by the side-wall spacers.

Abstract: The present invention proposes a novel structure of nonvolatile memories with recessed floating gates. A plurality of field oxides is formed on a semiconductor substrate. Buried bit lines are formed in the semiconductor substrate and beneath the field oxides. Between the field oxides over the buried bit lines, trenched floating gates are formed in the semiconductor substrate. Tunnel dielectrics are formed between the trenched floating gates and the semiconductor substrate. The interpoly dielectric is formed over the field oxides and the trenched floating gates and the control gates are formed on the interpoly dielectric. Because of the large area of the recessed tunnel dielectric and the recessed length of the channel, high-density shallow trench contactless nonvolatile memories can be achieved.

Abstract: A fork-shaped capacitor of a dynamic random access memory cell is disclosed. This capacitor includes a semiconductor layer (110), and a first dielectric layer (119) formed over the semiconductor layer. The capacitor also includes a first conductive region (118) formed on a portion of the first dielectric layer, the first conductive region communicating to the semiconductor layer via a hole in the first dielectric layer. At least two second conductive regions (122) are formed on the first conductive region, each of the conductive regions being spaced from each other. Further, at least two third conductive regions (126) are formed on the first dielectric layer, each of the third conductive regions being spaced from each other, each of the third conductive regions being spaced from each of the second conductive regions, wherein a portion of each of the third conductive regions abuts a sidewall of the first conductive region.

Abstract: A method to fabricate nonvolatile memories with a trench-pillar cell structure is disclosed. A pad oxide is formed on a substrate. A pad nitride is then formed on the pad oxide. An ion implantation is performed to form a lightly doping drain (LDD) in the substrate. The pad nitride, the pad oxide and the substrate are etched to form a trench. A nitride layer is then formed on the pad nitride to fill into the trench. The nitride layer is etched back to form spacers on the sidewalls of the trench. The substrate is etched back to form a subtrench in the trench. Afterward, a polysilicon layer is deposited to refill the trench region and covers a surface of the nitride. The polysilicon is etched back to remove the polysilicon layer on a surface of the nitride. The pad nitride, the nitride and the pad oxide are removed. A tunnel oxide is formed on the pillar, the trench region and the substrate. A floating gate is then formed. The floating is in the trench region and is extended to the top of the trench.

Abstract: The present invention includes a normal NMOS device region and a NMOS cell region for coding. An isolation structure is formed between the normal NMOS device region and the NMOS cell region. A gate oxide is formed on the normal NMOS device region and a coding oxide is formed on the NMOS cell region. A polysilicon layer is formed on the gate oxide. Gates are respectively formed on the polysilicon layer and the coding oxide. Spacers are formed on the side walls of the gates. LDD structures are formed under the spacers and adjacent to the gates. Source and drain regions are formed next to the LDD structures. A p type conductive region is formed adjacent to the surface of the NMOS cell region and under the coding oxide.

Abstract: An interconnection structure is disclosed. The interconnection structure has a dielectric layer over a semiconductor substrate. The interconnection structure also has first conductive connections within the dielectric layer. Second conductive connections are located over first conductive connections within the dielectric layer for connecting the first conductive connections. More layers of the interconnection structure can be stacked with the same structure to form multi-level connections.

Abstract: The method for forming a trench isolation includes the steps as follows. At first, a first pad layer is formed over the semiconductor substrate and a stacked layer is formed over the first pad layer. An opening is then defined in the first pad layer and the stacked layer. A portion of the first pad layer is removed to have an undercut region under the stacked layer. A second pad layer is formed on an exposed portion of the semiconductor substrate under the opening and the undercut region. Then a buffer layer within the undercut region and a sidewall structure on the stacked layer are formed. A portion of the second pad layer uncovered by the sidewall structure is removed. A portion of the semiconductor substrate uncovered by the stacked layer and the second pad layer is then removed to form a trench. A first insulator layer is formed over the trench and within the undercut region. Thus a trench structure with a first insulator layer can be formed.

Abstract: The process includes the following steps. At first, an isolation region in the semiconductor substrate is formed to separate the semiconductor substrate into a PMOS region, a NMOS region, and an ESD protective region. Gate structures are then formed on the PMOS region, the NMOS region, and the ESD protective region. A doping process is performed to the NMOS region and the ESD protective region, with first dopants for a lightly doped region in the semiconductor substrate. Another doping process is performed to the PMOS region and the ESD protective region, with second dopants for a PMOS anti-punchthrough region and an ESD double diffused region. Spacer structures are formed around the gate structures. The NMOS region and the ESD protective region are then doped with third dopants, for a n-junction region in the semiconductor substrate uncovered by the gate structures. The PMOS region is doped with fourth dopants for a p-junction region in the semiconductor substrate uncovered by the gate structures.

Abstract: A method of fabricating a trench-isolation structure is provided. The fabricated trench-isolation structure in accordance with the present invention is formed on a semiconductor substrate. Sequentially, a buffer layer and a first isolating layer are formed to overlie the semiconductor substrate. After the first isolating layer is patterned to form an opening, the step of forming spacers on the sidewall of the opening follows. At the same time, within the range of the opening the portion of the buffer layer not covered by the spacers is removed to expose a portion of the semiconductor substrate. Then, the exposed semiconductor substrate is etched to form a trench. After a second isolating layer is formed on the peripherals of the trench, an isolation plug is filled in the trench.

Abstract: The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is formed over the first dielectric layer. Next, the photoresist layer is patterned to define a gate region. An etching process is performed to the photoresist layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual photoresist layer as a mask. The undoped polysilicon layer is etched by using the residual photoresist layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate.

Abstract: The present invention discloses a novel multiple fin-shaped capacitor for use in semiconductor memories. The capacitor has a plurality of horizontal fins and a crown shape. The capacitor structure comprises a bottom storage electrode. The bottom storage electrode comprises of a plurality of horizontal fins and a crown shape, wherein said crown shape includes two vertical pillars, and said plurality of horizontal fins extend outside from an external surface of said crown shape. A second dielectric layer is formed on the surface of the bottom storage electrode layer. A top storage electrode layer is formed along the surface of second dielectric layer. By including horizontal fins and vertical pillars, the surface area of the capacitor is significantly increased, resulting in increased capacitance.

Abstract: A method to simultaneously fabricate the self-aligned silicided devices and electrostatic discharge devices is disclosed. A substrate is provided, a functional region and an electrostatic discharge region are defined on the substrate, gates of the regions are formed, lightly doping drain is formed in the substrate, a pad silicon nitride is formed on the electrostatic discharge region, spacers of the functional region is formed, a refractory metal is deposited or sputtered on the functional region, a two-step salicide process is performed on the substrate and a salicide layer is formed on the surface of the functional region, a high-energy implantation is performed on the substrate to form the active regions of the functional device and the electrostatic discharge device, a thick field oxide is formed on the surface of the substrate and a rapid thermal processing anneal is performed on the substrate to form an ultra-shallow junction of the functional devices.

Abstract: The method of the present invention includes forming a silicon dioxide layer, a first conductive layer and a first oxide layer on a silicon substrate to define a gate region of transistors. Then, a pad oxide layer is formed on the silicon substrate and a second oxide layer is formed on a side of the first conductive layer. Subsequently, a nitride spacer and a third oxide layer are formed, respectively. Then, the third oxide layer and the first oxide layer are removed. Next, a first metal layer is deposited on the silicon substrate and a source/drain/gate implantation is performed via ion implantation. Subsequently, a silicidation process is used to convert portions of the first metal layer into a silicide layer and then unreacted portions of the first metal layer and the nitride spacer are removed. Next, an ion implantation is performed to form an extended source/drain junction. Then, a fourth oxide layer is formed.

Abstract: The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is formed over the nitride layer and a first silicon layer is formed over the second oxide layer. Next, a node opening is defined in the first silicon layer, the second oxide layer, and the nitride layer, upon the first oxide layer. Sidewall structures are then formed on sidewalls of the node opening. A contact opening is then defined in the first oxide layer under the node opening. The contact opening is defined in the first oxide layer under a region uncovered by the sidewall structures. The sidewall structures and a portion of the nitride layer nearby the node opening are removed to form undercut structures under the second oxide layer.