Abstract: A memory data access structure and an access method suitable for use in a processor. For each instruction executed by the processor, the execution results are recognized by the processor and transferred to a cache memory via control signals. When the instruction to be fetched is not stored in the cache memory, according to the control signals, the cache memory can determine whether the instruction is to be fetched from an external memory. With such structure, no matter whether the processor comprises a branch prediction mechanism or not, many operation clock cycles consumed in the processor of the prior art are saved by compensating for the situation that the cache memory fails to fetch, that is, a Miss of the cache memory. The efficiency and performance of the processor can be effectively enhanced.

Abstract: A coprocessor data access control method having a coprocessor memory access instruction with a coprocessor indicating field such that the quantity of word data to be transmitted between the coprocessor and the memory unit can be determined. The coprocessor indicating field actually includes a coprocessor number field and a coprocessor register field. The coprocessor number field indicates the particular coprocessor to be used while the coprocessor register field indicates the particular registers to be used.

Abstract: In a fast response time pipelined data processor, an interrupt control device stores the interrupt service routine address or the target address of a branch instruction, as applicable, in a register. If an interrupt occurs while the pipelined data processor is processing a branch instruction, the branch instruction target address stored in the register is used as the return address, and is stored in a working space, so that the interrupt can be processed immediately. Similarly, if an interrupt occurs while the pipelined data processor is processing a prior interrupt or exception, and the first instruction of the interrupt service routine of the previous interrupt has not yet reached the memory access stage, the interrupt service routine as address of the previous interrupt stored in the register is used as the return address, and is stored in the working space, so that the next interrupt can be processed immediately.