Abstract: An active mixer with self-adaptive bias feedback is described and resolves a poor linearity, inconvenient design of a bias circuit, and other defects of a conventional mixer. The dual self-feedback bias structure according to this invention is used. The active mixer with self-adaptive bias feedback has a power supply, an RF input match/drive unit, a local oscillator input match/drive unit, a mixer core unit, a self-adaptive twin bias circuit and an IF output match/buffer unit. This invention improves the linearity of a conventional mixer and does not affect other characteristics. There are fewer components in this invention; an area of the mixer is thus smaller. Further, this invention may improve temperature response, increase yield factor, and lower unit cost. The dual self-feedback bias structure is designed for further application to other semiconductor manufacturing processes, components, and microwave products.

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract: A high-gain and low-noise low noise amplifier (LNA) includes a differential amplifier, a pre-amplifier and an impedance matching network. The differential amplifier includes a first input end and a second input end coupled to a grounded impedance. The pre-amplifier includes an input end and an output end. The impedance matching network is coupled between the first input end of the differential amplifier and the output end of the pre-amplifier for matching an input impedance of the differential amplifier with an output impedance of the pre-amplifier. The present invention provides a LNA structure with low noise, high gain and easy design.

Abstract: A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first resistor element, a second resistor element, a third resistor element, a fourth resistor element, and a fifth resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide, such as titanium silicide or cobalt silicide, using a silicidation process. The higher conductivity silicide forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements.

Abstract: Described is a method where a seal ring is formed by stacking interconnected conductive layers along the perimeter of an integrated circuit (IC). The seal ring is formed continuously around the IC perimeter using a conductive chain with two distinct widths. Each section of distinct width forms a transmission having a distinct characteristic impedance. Unwanted signals may be coupled to the seal ring from signal bond pads or from internal circuitry. Because of the impedance mismatch between the different width sections of the seal ring transmission lines, only a portion of each signal is propagated through each seal ring discontinuity while the remainder is reflected. As the signal passes through multiple discontinuities in the seal ring, it is further attenuated, reducing propagation of unwanted signals. This is accomplished while preventing moisture intrusion into the IC.

Abstract: Described is a method where a seal ring is formed by stacking interconnected conductive layers along the perimeter of an integrated circuit (IC). The seal ring is formed continuously around the IC perimeter using a conductive chain with two distinct widths. Each section of distinct width forms a transmission having a distinct characteristic impedance. Unwanted signals may be coupled to the seal ring from signal bond pads or from internal circuitry. Because of the impedance mismatch between the different width sections of the seal ring transmission lines, only a portion of each signal is propagated through each seal ring discontinuity while the remainder is reflected. As the signal passes through multiple discontinuities in the seal ring, it is further attenuated, reducing propagation of unwanted signals. This is accomplished while preventing moisture intrusion into the IC.

Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

Abstract: A method and structure for a compact transistor array layout is applied in a bipolar transistor integration process for equalizing distributed reactance in a wafer. The structure has a plurality of unitization elements with a first element and a second element for receiving an input signal. The first element and the second element are composed of a plurality of transistors. A plurality of wires used to feed the input signal in the unitization elements are arranged in multi-level branches manner. The wires can have predetermined resistance, capacitance, or inductance and the input signal is equidistant from the unitization elements. A multi-dimensional layout space is formed by arranging the unitization elements in order. The inventive structure can be applied in heterojunction bipolar transistor (HBT) or bipolar junction transistor (BJT) so that more transistors can be installed in a unit volume.

Abstract: Method and apparatus determine the performance of an integrated circuit that includes at least one of a plurality of deep-well trench dynamic random-access memory (DRAM) cells. The method includes executing a circuit simulator for designing an integrated circuit that contains at least one of a plurality of DRAM cells. Further, the method includes calculating a set of output parameters with the circuit simulator for each of the plurality of DRAM cells utilizing, for example, a deep-well trench DRAM cell model for each of the plurality of DRAM cells.

Abstract: Described is a method where a seal ring is formed by stacking interconnected conductive layers along the perimeter of an integrated circuit (IC). The seal ring is formed continuously around the IC perimeter using a conductive chain with two distinct widths. Each section of distinct width forms a transmission having a distinct characteristic impedance. Unwanted signals may be coupled to the seal ring from signal bond pads or from internal circuitry. Because of the impedance mismatch between the different width sections of the seal ring transmission lines, only a portion of each signal is propagated through each seal ring discontinuity while the remainder is reflected. As the signal passes through multiple discontinuities in the seal ring, it is further attenuated, reducing propagation of unwanted signals. This is accomplished while preventing moisture intrusion into the IC.

Abstract: A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first resistor element, a second resistor element, a third resistor element, a fourth resistor element, and a fifth resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide, such as titanium silicide or cobalt silicide, using a silicidation process. The higher conductivity silicide forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements.

Abstract: A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.

Abstract: A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: A semiconductor device having an inductor including a planar coil portion forming an opening in the center thereof and a core received in the opening and extending above and below the planar coil portion. A first and a second inter-metal dielectric layer, and the inductor further including a first connecting leg including an electrically conductive material. The first connecting leg is connected to the planar coil portion. The planar coil portion is in the first inter-metal dielectric layer and the first connecting leg is in the second inter-metal dielectric layer. The inductor further includes a second connecting leg connected to the planar coil portion, and an electrically conductive bump connected to the second connecting leg.

Abstract: Within both a method for fabricating a microelectronic inductor structure, and the microelectronic inductor structure fabricated employing the method, there is formed over a substrate a spirally patterned conductor layer. Within both the method and the microelectronic inductor structure there is also formed over the substrate and annularly surrounding the spirally patterned conductor layer an annular magnetic shielding layer.

Abstract: A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias.

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.