Patents by Inventor Shyh-Chyi Wong
Shyh-Chyi Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030096473Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.Type: ApplicationFiled: November 16, 2001Publication date: May 22, 2003Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Wong-Cheng Shih, Wenchi Ting, Tzyh-Cheang Lee, Chin-Hsien Lin, Shyh-Chyi Wong
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Patent number: 6559493Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.Type: GrantFiled: June 11, 2002Date of Patent: May 6, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tzyh-Cheang Lee, Shyh-Chyi Wong, Chih-Hsien Lin, Chi-Feng Huang
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Publication number: 20030076209Abstract: A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias.Type: ApplicationFiled: September 10, 2001Publication date: April 24, 2003Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Chao Chieh Tsai, Shyh-Chyi Wong
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Publication number: 20030008450Abstract: A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.Type: ApplicationFiled: September 6, 2002Publication date: January 9, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chaochieh Tsai, Chung-Long Chang, Julyu Chang, Shyh-Chyi Wong
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Patent number: 6501137Abstract: An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type semiconductor layer. The PMOS device, integrated with the semiconductor-controlled rectifier to share a first P-type doped region, has a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the electrostatic discharge power, the PNP device will conduct to trigger the semiconductor-controlled rectifier.Type: GrantFiled: August 7, 2000Date of Patent: December 31, 2002Assignee: Winbond Electronics Corp.Inventors: Ta-Lee Yu, Shyh-Chyi Wong
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Publication number: 20020190346Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.Type: ApplicationFiled: August 23, 2002Publication date: December 19, 2002Applicant: Winbond Electronics CorporationInventors: Shyh-Chyi Wong, Wen-Ying Wen
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Publication number: 20020177271Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.Type: ApplicationFiled: June 11, 2002Publication date: November 28, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Tzyh-Cheang Lee, Shyh-Chyi Wong, Chih-Hsien Lin, Chi-Feng Huang
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Patent number: 6480414Abstract: A multi-level memory cell has a substrate, a first floating gate, a second floating gate and a control gate. A first doped region, a second doped region and a channel region located between the first doped region and the second doped region are provided in the substrate. The first floating gate is located over the channel region near the first doped region. The second floating gate is located over the channel region near the second doped region and isolated from the first floating gate. A control gate is located over the first and the second floating gates. When writing operations are proceeding, the bias voltages of the control gates are the same, and a constant bias voltage is provided on the first doped region or the second doped region depending on which binary states 11, 10, 01 or 00 are to write. Furthermore, the same bias voltage is used on the control gate during writing operation. Thus, the memory per unit chip area is enhanced and the peripheral circuits are simplified.Type: GrantFiled: June 5, 2000Date of Patent: November 12, 2002Assignee: Winbond Electronics Corp.Inventors: Hong Chin Lin, Shyh-Chyi Wong, Tai-Yuan Chen
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Patent number: 6476451Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.Type: GrantFiled: March 20, 2001Date of Patent: November 5, 2002Assignee: Winbond Electronics CorporationInventor: Shyh-Chyi Wong
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Patent number: 6469362Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.Type: GrantFiled: February 15, 2000Date of Patent: October 22, 2002Assignee: Winbond Electronics Corp.Inventors: Shyh-Chyi Wong, Wen-Ying Wen
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Patent number: 6465294Abstract: A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.Type: GrantFiled: March 16, 2001Date of Patent: October 15, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chaochieh Tsai, Chung-Long Chang, Ju-Yu Chang, Shyh-Chyi Wong
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Patent number: 6459613Abstract: A current-mode identifying circuit includes a current duplicating circuit for duplicating a cell current, which flows through a selected flash cell in a multilevel flash memory, and for outputting multiple duplicate cell currents. Each of multiple reference current generating units draws a predetermined reference current from a respective duplicate cell current to form a difference current. Each of multiple current comparators receives the difference current from a corresponding reference current generating unit, and outputs a logic signal corresponding to magnitude of the difference current. An encoder encodes the logic signals from the current comparators to identify a level associated with the cell current.Type: GrantFiled: October 29, 2001Date of Patent: October 1, 2002Assignee: Winbond Electronics CorporationInventors: Hongchin Lin, Chein-Zhi Chen, Shyh-Chyi Wong
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Patent number: 6444517Abstract: A new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second layer of metal form an inductor of increased height, reducing the resistivity of the inductor, increasing the Q value of the inductor. The new method of creating an inductor can be combined with creating contact points that connect to contact points in the active region of the surface of a semiconductor substrate.Type: GrantFiled: January 23, 2002Date of Patent: September 3, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Heng-Ming Hsu, Shyh-Chyi Wong, Chaochieh Tsai, Ssu-Pin Ma, Chao-Cheng Chen, Liang-Kun Huang
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Patent number: 6436787Abstract: A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening.Type: GrantFiled: July 26, 2001Date of Patent: August 20, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wong-Cheng Shih, Tzyh-Cheang Lee, Wenchi Ting, Chih-Hsien Lin, Shyh-Chyi Wong
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Publication number: 20020105363Abstract: The present invention discloses a current comparator having simple, cheap and fast characteristics, especially discloses a current comparator having a small dead zone and excellent driving capability. The current comparator of the present invention comprises a first CMOS transistor, a second CMOS transistor, a diode-configured N-type transistor, a fourth CMOS transistor and a fifth CMOS transistor.Type: ApplicationFiled: June 26, 2001Publication date: August 8, 2002Inventors: Hong-Chin Lin, Jie-Hau Haung, Shyh-Chyi Wong
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Patent number: 6426250Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.Type: GrantFiled: May 24, 2001Date of Patent: July 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tzyh-Cheang Lee, Shyh-Chyi Wong, Chih-Hsien Lin, Chi-Feng Huang
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Patent number: 6424183Abstract: The present invention discloses a current comparator having simple, cheap and fast characteristics, especially discloses a current comparator having a small dead zone and excellent driving capability. The current comparator of the present invention comprises a first CMOS transistor, a second CMOS transistor, a diode-configured N-type transistor, a fourth CMOS transistor and a fifth CMOS transistor.Type: GrantFiled: June 26, 2001Date of Patent: July 23, 2002Assignee: Windbond Electronics CorporationInventors: Hong-Chin Lin, Jie-Hau Huang, Shyh-Chyi Wong
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Publication number: 20020093414Abstract: A semiconductor device including a substrate, a polysilicon shield layer having a plurality of dielectric sections disposed over the substrate and the plurality of dielectric sections being of a geometric shape, and an inductor including a first metallic layer disposed over the polysilicon layer wherein the first metallic layer overlaps a number of the plurality of dielectric sections and each of the plurality of dielectric sections is of a proximity from one another to substantially reduce or prevent mirror current from being formed in the shield layer.Type: ApplicationFiled: January 17, 2001Publication date: July 18, 2002Applicant: Winbond Electronics CorporationInventors: Shyh-chyi Wong, Chiung-Ting Ou
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Patent number: 6414361Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.Type: GrantFiled: January 5, 2001Date of Patent: July 2, 2002Assignee: Winbond Electronics CorporationInventors: Shyh-Chyi Wong, Shi-Tron Lin
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Publication number: 20020070806Abstract: An ATG MOSFET is constructed of a plurality of ATG MOSFET elements each including a gate region. One of a source and drain region of each ATG MOSFET element is shared in common with an adjacent one of the ATG MOSFET elements. The plurality of ATG MOSFET elements are connected in parallel to provide a desired driving current capacity and reduced effective driving capacitance. The ATG MOSFET is implemented in a high frequency RF amplifier.Type: ApplicationFiled: June 30, 1999Publication date: June 13, 2002Inventors: SHYH-CHYI WONG, CHI-HUNG KAO