Abstract: A structure is disclosed for a multi-finger transistor with improved high frequency performance. An array of isolated active regions is formed in a semiconductor substrate. A source region and a drain region are formed in each of the active regions and are disposed on either side of a central channel region. A gate oxide layer is formed over each channel region. Conductive gate fingers that extend over the gate oxide layers and also beyond the active areas are formed so that each gate finger constitutes a continuous conductive line providing and connecting the gates of the plurality of active regions. A dielectric layer is formed over the active regions and over the surrounding isolation regions. A conductive via is formed through the dielectric layer to each source region and to each drain region. For each gate finger or conductive via is opened between the active region and at both ends of the finger contact region is formed over each conductive via.

Abstract: A method for forming anchored bond pads on a semiconductor substrate and a semiconductor device containing such anchored bond pads are described. In the method, a plurality of via openings is first formed in a dielectric material layer on top of a semiconductor substrate. A metal is then filled into the plurality of via openings forming a plurality of via contacts and a bond pad on top of the dielectric material layer intimately connected to the plurality of via contacts. After the bond pad is defined by a photolithographic method, a bond pad that is anchored to the dielectric material layer by a plurality of via contacts is thus obtained. In an alternate embodiment, a first metal is used to form the plurality of via contacts, while a second metal is used to form the bond pad layer. A suitable first metal may be a refractory metal, while a suitable second metal may be aluminum or aluminum alloys. The first metal and the second metal may also be of the same material such as copper or a copper alloy.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: The present invention relates to a charge-pumping circuit for low-supply voltage. A small charge-pumping circuit was added at the gates of the original Dickson charge-pumping circuit's each stage for bias voltage and the first transistor group was added between well and gate. The second transistor group was added between the gate and drain of original transistor. Thus, the charge-pumping circuit for low-supply voltage can supply a higher positive or negative voltage.

Abstract: A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N− LDS/LDD regions in the P-well. Form N− LDS/LDD regions in the P-well and P− lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N− LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P− LDS/LDD regions in the N-well in the source/drain sites.

Abstract: A SOI device structure is formed on a SOI substrate having a body contact. The SOI substrate has an insulating layer thereon and a silicon layer is disposed on the insulating layer. A gate is disposed on the silicon layer. A source region and a drain region are respectively disposed within the silicon layer beside the gate. A body contact is provided at an interface between the insulating layer and the silicon layer wherein the body contact is preferably located between the source region and the gate. The body contact, disposed between the source region and the gate can reduce kink effect and body effect, thereby enhancing the performance of device formed on SOI.

Abstract: The present invention relates to a charge-pumping circuit for low-supply voltage. A small charge-pumping circuit was added at the gates of the original Dickson charge-pumping circuit's each stage for bias voltage and the first transistor group was added between well and gate. The second transistor group was added between the gate and drain of original trans0istor. Thus, the charge-pumping circuit for low-supply voltage can supply a higher positive or negative voltage.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: An interface buffer circuit connected at an interface of circuits having a high voltage power supply and circuits having a low voltage power supply, prevents damage due to application of the high voltage power supply to the output terminal of the interface buffer circuit. The interface buffer circuit has a predriver circuit and an interface buffer circuit. The interface buffer circuit has an interface buffer protection circuit. The interface buffer protection circuit consists of an inverter circuit. The inverter circuit has an input connected to the input of the interface driver circuit and an output connected to the gate of a MOS transistor. The source of the MOS transistor is connected to the predriver circuit to control the output of the predriver circuit. The interface buffer protection circuit further has a coupling capacitor connected to interface driver circuit.

Abstract: This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.

Abstract: A dynamic threshold voltage MOSFET to provide increase drain-to-source saturation current (I.sub.DSsat) and lower off current (I.sub.off) is described. The dynamic threshold voltage MOSFET has a first diffusion-well of a material of a first conductivity type formed at the surface of the substrate to form a bulk region. A source region and a drain region of a material of a second conductivity type are diffused into the diffusion-well. A first gate is then placed on a first oxide surface above the substrate between the source and drain regions. An accumulated base bipolar transistor is then placed on the semiconductor substrate. The base of the accumulated base bipolar transistor is connected to the gate, the emitter is connected to the diffusion-well. A resistor is connected between the emitter of the accumulated base bipolar transistor and a substrate biasing voltage source.

Abstract: A circuit and a method for measuring the read operation delay on DRAM bit lines are disclosed. The circuit comprises a plurality of circuit blocks connected in series, each having a 1-bit DRAM cell. The output of the DRAM cell in each circuit block is connected to the word line of the DRAM cell of the next circuit block through inverters, so the read operation in the DRAM cell of the next circuit block is triggered. The total delay between the word line at the first circuit block and the output of the last circuit block can be measured on the oscilloscope. The delay for every 1-bit DRAM cell is equal to the total delay divided by the number of circuit blocks.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the V.sub.dd and V.sub.ss power rails caused by the latchup of parasitic and complementary bipolar transistor structures that are present in CMOS devices. These goals have been achieved without the use of guard rings by using p-region implants in the n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors. Further, the p-region implants are shorted to a reference voltage V.sub.ss via a p.sup.+ ground tab thus backbiasing the diode-like p-region implants. The proposed methods are compatible with CMOS processes.

Abstract: A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N- LDS/LDD regions in the P-well. Form N- LDS/LDD regions in the P-well and P- lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N- LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P- LDS/LDD regions in the N-well in the source/drain sites.

Abstract: A semiconductor integrated circuit includes a first charge pumping circuit connected to an input node. The first charge pump circuit includes a plurality of first driving transistors and charges an input voltage at the input node to a control voltage. A second charge pumping circuit includes a plurality of second driving transistors that each receive the control voltage from the first charge pump. The received control voltage controls the driving of the second transistors when charging an output node to an output voltage. To eliminate body effects, the semiconductor integrated circuit further includes a plurality of body transistors that connect the source and body terminals of the driving transistors.