Patents by Inventor Silvia M. Mueller

Silvia M. Mueller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10929213
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
  • Patent number: 10915385
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
  • Publication number: 20200264842
    Abstract: Performing processing using hardware counters in a computer system includes storing, in association with greatest common divisor (GCD) processing of the system, a first variable in a first redundant binary representation and a second variable in a second redundant binary representation. Each such redundant binary representation includes a respective sum term and a respective carry term, and a numerical value being represented by a redundant binary representation is equal to a sum of the sum and carry terms of the redundant binary representation. The process performs redundant arithmetic operations of the GCD processing on the first variable and second variables using hardware counter(s), of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form. The process uses output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Inventors: Eric M. SCHWARZ, Silvia M. MUELLER, Ulrich MAYER
  • Publication number: 20200264840
    Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Cedric LICHTENAU, Reid COPELAND, Petra LEBER, Silvia M. MUELLER, Jonathan D. BRADBURY, Xin GUO
  • Publication number: 20200264890
    Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Cedric LICHTENAU, Reid COPELAND, Petra LEBER, Silvia M. MUELLER, Jonathan D. BRADBURY, Xin GUO
  • Patent number: 10740098
    Abstract: A method, computer program product, and computer system for providing a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m is provided. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
  • Patent number: 10713056
    Abstract: A non-limiting example of a computer-implemented method for implementing wide vector execution for an out-of-order processor includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Silvia M. Mueller, Mauricio J. Serrano, Balaram Sinharoy
  • Patent number: 10705847
    Abstract: A non-limiting example of a computer-implemented method for implementing wide vector execution for an out-of-order processor includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Silvia M. Mueller, Mauricio J. Serrano, Balaram Sinharoy
  • Patent number: 10649738
    Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Klaus M. Kroener, Silvia Melitta Mueller, Andreas Wagner
  • Patent number: 10649730
    Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
  • Patent number: 10592208
    Abstract: A specialized circuit is configured for floating point computations using numbers represented by a very low precision format (VLP format). The VLP format includes less than sixteen bits and is apportion into a sign bit, exponent bits (e), and mantissa bits (p). The configured specialized circuit is operated to store an approximation of a numeric value in the VLP format, where the approximation is represented as a function of a multiple of a fraction, where the fraction is an inverse of a number of discrete values that can be represented using only the mantissa bits.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naigang Wang, Kailash Gopalakrishnan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Daniel Brand
  • Patent number: 10579375
    Abstract: The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
  • Patent number: 10572223
    Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
  • Patent number: 10558432
    Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Tina Babinsky, Michael Klein, Cedric Lichtenau, Silvia M. Mueller
  • Publication number: 20190339938
    Abstract: A specialized circuit is configured for floating point computations using numbers represented by a very low precision format (VLP format). The VLP format includes less than sixteen bits and is apportion into a sign bit, exponent bits (e), and mantissa bits (p). The configured specialized circuit is operated to store an approximation of a numeric value in the VLP format, where the approximation is represented as a function of a multiple of a fraction, where the fraction is an inverse of a number of discrete values that can be represented using only the mantissa bits.
    Type: Application
    Filed: May 7, 2018
    Publication date: November 7, 2019
    Applicant: International Business Machines Corporation
    Inventors: NAIGANG WANG, Kailash Gopalakrishnan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Daniel Brand
  • Patent number: 10459689
    Abstract: Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Klaus M. Kroener, Silvia Melitta Mueller, Manuela Niekisch, Kerstin Schelm
  • Publication number: 20190317726
    Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Inventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
  • Patent number: 10416962
    Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Juergen Haess, Michael Klein, Klaus M. Kroener, Petra Leber, Silvia M. Mueller, Kerstin Schelm
  • Patent number: 10379859
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 10379811
    Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner