Patents by Inventor Silvia M. Mueller
Silvia M. Mueller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10379859Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: May 3, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 10379860Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: May 3, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Publication number: 20190243649Abstract: The present disclosure relates a method, computer program product, and computer system to provide a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.Type: ApplicationFiled: February 6, 2018Publication date: August 8, 2019Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
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Publication number: 20190243650Abstract: The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.Type: ApplicationFiled: February 6, 2018Publication date: August 8, 2019Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
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Patent number: 10372417Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.Type: GrantFiled: July 13, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Tina Babinsky, Michael Klein, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20190212983Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Patent number: 10331407Abstract: A method for performing tiny detection in floating-point operations with a floating-point unit. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.Type: GrantFiled: November 11, 2017Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
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Patent number: 10310936Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.Type: GrantFiled: January 12, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
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Patent number: 10310815Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: GrantFiled: November 30, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Publication number: 20190163445Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Patent number: 10303563Abstract: An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.Type: GrantFiled: September 14, 2016Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Silvia M. Mueller, Manuela Niekisch, Kerstin Schelm
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Patent number: 10303438Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.Type: GrantFiled: January 16, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tina Babinsky, Udo Krautz, Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner
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Patent number: 10296294Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.Type: GrantFiled: February 15, 2018Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Tina Babinsky, Michael Klein, Cedric Lichtenau, Silvia M. Mueller
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Patent number: 10241756Abstract: A floating-point unit for performing tiny detection in floating-point operations. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.Type: GrantFiled: July 11, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
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Patent number: 10235135Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.Type: GrantFiled: July 17, 2017Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
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Patent number: 10228910Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.Type: GrantFiled: May 1, 2018Date of Patent: March 12, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20190042265Abstract: Embodiments of the present invention include methods, systems, and computer program products for implementing wide vector execution in a single thread mode for an out-of-order processor. A non-limiting example of the computer-implemented method includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.Type: ApplicationFiled: August 1, 2017Publication date: February 7, 2019Inventors: Silvia M. Mueller, Mauricio J. Serrano, Balaram Sinharoy
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Publication number: 20190042266Abstract: Embodiments of the present invention include methods, systems, and computer program products for implementing wide vector execution in a single thread mode for an out-of-order processor. A non-limiting example of the computer-implemented method includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.Type: ApplicationFiled: November 8, 2017Publication date: February 7, 2019Inventors: Silvia M. Mueller, Mauricio J. Serrano, Balaram Sinharoy
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Patent number: 10198302Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.Type: GrantFiled: December 29, 2017Date of Patent: February 5, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
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Publication number: 20190018654Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.Type: ApplicationFiled: December 28, 2017Publication date: January 17, 2019Inventors: Tina Babinsky, Michael Klein, Cedric Lichtenau, Silvia M. Mueller