Abstract: A method for performing tiny detection in floating-point operations with a floating-point unit. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.

Abstract: A floating-point unit for performing tiny detection in floating-point operations. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.

Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.

Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.

Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.

Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.

Abstract: A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.

Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.