Abstract: Software that provides a subset of error correcting code (ECC) bits to be used for parity purposes. The software performs the following steps: (i) providing, in a data block, a first set of redundant bits adapted to detect and correct errors in the data block, based, at least in part, on a first set of error detection/correction (EDC) requirements; and (ii) providing, within the first set of redundant bits, a first sub-set of parity bit(s) adapted to provide single bit error detection for the data block. The EDC requirements include: (i) a minimum hamming distance, and (ii) the bit(s) in the first set of redundant bits that are not in the first sub-set of parity bit(s) include enough bit(s) to create at least P unique (M-2)-tuples, where P equals the number of bits in the first sub-set of parity bits, and where M equals the minimum hamming distance.

Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: A tool for supporting vector operations in a scalar data path. The tool determines a location for a split in the scalar mode configuration to enable vector mode operations. The tool determines the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration. The tool receives a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration.

Abstract: A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.

Abstract: A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

Abstract: A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.

Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.