Patents by Inventor Simon Chooi

Simon Chooi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7452808
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 18, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Patent number: 7268048
    Abstract: Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: September 11, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yin-Min Felicia Goh, Simon Chooi, Teck Wee Lim, Vincent Sih, Chian Yuh Sin, Ping Yu Ee, Zainab Ismail, Cher Sian Chua
  • Patent number: 7186640
    Abstract: A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: March 6, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Liu Huang, John Sudijono, Simon Chooi
  • Patent number: 7179879
    Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: February 20, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi, Mei Sheng Zhou
  • Patent number: 7166250
    Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: January 23, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi, Mei Sheng Zhou
  • Patent number: 7078333
    Abstract: Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the low dielectric constant material layer. Thereafter, a TEOS-based silicon oxide layer is deposited overlying the low dielectric constant material whereby there is good adhesion between low dielectric constant material layer and the TEOS-based silicon oxide layer. In another method, a low dielectric constant material layer is deposited on a substrate. A silicon-based dielectric layer is deposited overlying the low dielectric constant material wherein the silicon-based dielectric layer is not silicon oxide whereby there is good adhesion between the low dielectric constant material layer and the silicon-based dielectric layer.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: July 18, 2006
    Inventors: Luona Goh, Simon Chooi, Siew Lok Toh, Tong Earn Tay
  • Patent number: 7071281
    Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: July 4, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi, Mei Sheng Zhou
  • Patent number: 7060613
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: June 13, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Xu Yi
  • Patent number: 7005716
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: February 28, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Publication number: 20060030095
    Abstract: Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation.
    Type: Application
    Filed: August 6, 2004
    Publication date: February 9, 2006
    Inventors: Yin-Min Goh, Simon Chooi, Teck Lim, Vincent Sih, Chian Sin, Ping Ee, Zainab Ismail, Cher Chua
  • Patent number: 6987321
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: January 17, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6967162
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 22, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20050159576
    Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
    Type: Application
    Filed: January 4, 2005
    Publication date: July 21, 2005
    Inventors: Christopher Lim, Siu Ng, Hardy Chan, Simon Chooi, Mei Zhou
  • Publication number: 20050124767
    Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
    Type: Application
    Filed: January 4, 2005
    Publication date: June 9, 2005
    Inventors: Christopher Lim, Siu Ng, Hardy Chan, Simon Chooi, Mei Zhou
  • Publication number: 20050119420
    Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
    Type: Application
    Filed: January 4, 2005
    Publication date: June 2, 2005
    Inventors: Christopher Lim, Siu Ng, Hardy Chan, Simon Chooi, Mei Zhou
  • Publication number: 20050112799
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 26, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu
  • Patent number: 6891233
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 10, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Publication number: 20050090037
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: October 29, 2004
    Publication date: April 28, 2005
    Inventors: Yakub Aliyu, Simon Chooi, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy
  • Publication number: 20050090039
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: April 28, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20050090102
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: April 28, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu