Abstract: A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

Abstract: A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with silicon can also be etched with the addition of a fluorine-containing or chlorine-containing gas. A semiconductor substrate is provided. A low dielectric constant organic-based material is deposited overlying the semiconductor substrate. The low dielectric constant organic-based material is etched to form desirable features using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule, and the integrated circuit device is completed.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: A new apparatus is provided for the quantification of the adhesion of a film over a substrate. In particular, the peeling force and the rate of peeling are quantified by providing a first means for measuring the peeling force, a second means for measuring the rate of peeling, a third means for securing a piece of wafer, an adhesive tape, a tape holder and a resilient, flexible component.

Abstract: Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the low dielectric constant material layer. Thereafter, a TEOS-based silicon oxide layer is deposited overlying the low dielectric constant material whereby there is good adhesion between low dielectric constant material layer and the TEOS-based silicon oxide layer. In another method, a low dielectric constant material layer is deposited on a substrate. A silicon-based dielectric layer is deposited overlying the low dielectric constant material wherein the silicon-based dielectric layer is not silicon oxide whereby there is good adhesion between the low dielectric constant material layer and the silicon-based dielectric layer.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A new method of forming a metal oxide high dielectric constant layer in the manufacture of an integrated circuit device has been achieved. A substrate is provided. A metal oxide layer is deposited overlying the substrate by reacting a precursor with an oxidant gas in a chemical vapor deposition chamber. The metal oxide layer may comprise hafnium oxide or zirconium oxide. The precursor may comprise metal alkoxide, metal alkoxide containing halogen, metal &bgr;-diketonate, metal fluorinated &bgr;-diketonate, metal oxoacid, metal acetate, or metal alkene. The metal oxide layer is annealed to cause densification and to complete the formation of the metal oxide dielectric layer in the manufacture of the integrated circuit device. A composite metal oxide-silicon oxide (MO2-SiO2) high dielectric constant layer may be deposited using a precursor comprising metal tetrasiloxane.

Abstract: A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing product. The reactant gas preferably contains sulfur and oxygen. The reactant gas more preferably comprises sulfur dioxide or sulfur trioxide. The reactant gas is preferably heated and optionally exposed to a plasma. Next, the metal containing product is removed using a liquid, thereby removing at least portion of the metal layer from over the substrate.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.

Abstract: An endpoint detection system for copper stripping using a colorimetric analysis of the change in concentration of a component is described, Wet copper stripping chemicals are used to strip copper from a wafer whereby an eluent is produced. The eluent is continuously analyzed by colorimetric analysis for the presence of copper. The copper stripping process is stopped when the presence of copper is no longer detected. Also novel compounds or chemicals for use in an endpoint detection system for copper stripping using a colorimetric analysis of the change in concentration of the novel compounds or chemicals are described. A composition of matter that serves as an indicator of the presence of copper by colorimetric analysis comprises: 1) Fast Sulphon Black F indicator and an ammonium ion-containing solution or 2) a complexing agent, comprising a diamine, an amine macrocycle, or a monoamine.

Abstract: A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure—single, dual, or multi-structure—is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

Abstract: Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.