Patents by Inventor Simon Chooi
Simon Chooi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040029321Abstract: A method of forming a dielectric layer on a semiconductor substrate, comprised with multiple dielectric constants and multiple equivalent oxide thicknesses (EOT), has been developed. After formation of a high dielectric constant (high k), layer, on a semiconductor substrate, a first region of the high k layer is subjected to a process directed at incorporating elements into a top portion of the high k layer, while a second region of the high k layer remains protected during this procedure. An anneal treatment results in the processed high k layer now exhibiting a different dielectric constant, as well as a different EOT, than the unprocessed, second region of the high k layer, not exposed to the above procedures.Type: ApplicationFiled: August 7, 2002Publication date: February 12, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Liang Choo Hsia, Jia Zhen Zheng, Soh Yun Siah, Simon Chooi
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Patent number: 6690091Abstract: A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and the cap layers comprise low dielectric constant materials carbon nitride, boron nitride, or boron carbon nitride. The stack is patterned to form a via opening to the first conductive layer. A trench opening is formed stopping on the etch stop layer. A barrier layer of TaN, WN, TaSiN or Ta and a second conductive material is applied to the openings. Passivation, etch stop, or cap layers can be formed with carbon nitride by magnetron sputtering from a graphite target in a nitrogen atmosphere; boron carbon nitride by magnetron sputtering from a graphite target in a nitrogen and B2H6 atmosphere; or boron nitride by PECVD using B2H6, ammonia, and nitrogen.Type: GrantFiled: September 21, 2000Date of Patent: February 10, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yi Xu, Mei Sheng Zhou
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Patent number: 6683002Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: GrantFiled: August 10, 2000Date of Patent: January 27, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6677652Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.Type: GrantFiled: August 26, 2002Date of Patent: January 13, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
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Publication number: 20030235980Abstract: A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.Type: ApplicationFiled: June 20, 2002Publication date: December 25, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Liu Huang, John Sudijono, Simon Chooi
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Patent number: 6638365Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.Type: GrantFiled: October 9, 2001Date of Patent: October 28, 2003Assignees: Chartered Semiconductor Manufacturing Ltd., Institute of Materials Research and EngineeringInventors: Jianhui Ye, Simon Chooi, Alex See
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Publication number: 20030196989Abstract: A method for forming a copper containing microelectronic structure. There is first provided a substrate. There is then formed over the substrate a copper containing microelectronic structure comprising a copper containing layer and a non-copper containing layer, where the non-copper containing layer has formed thereupon a copper containing residue. Finally, there is then stripped from the non-copper containing layer the copper containing residue while employing a stripper composition comprising a non-aqueous coordinating solvent and a halogen radical producing specie. Additionally, the copper so dissolved may be recovered from a non-aqueously solvated copper halide compound dissolved within the non-aqueous solvent.Type: ApplicationFiled: June 10, 2003Publication date: October 23, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Mei Sheng Zhou, Simon Chooi, Guo Qin Xu
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Publication number: 20030192943Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.Type: ApplicationFiled: April 11, 2002Publication date: October 16, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6602801Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.Type: GrantFiled: November 13, 2001Date of Patent: August 5, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Siew Yong Kong, Alex See, Simon Chooi, Gautam Sarkar
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Publication number: 20030140943Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: ApplicationFiled: February 3, 2003Publication date: July 31, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6565664Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.Type: GrantFiled: April 24, 2002Date of Patent: May 20, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Subhash Gupta, Simon Chooi, Paul Ho, Mei Sheng Zhou
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Patent number: 6566260Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.Type: GrantFiled: August 10, 2001Date of Patent: May 20, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
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Publication number: 20030092240Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.Type: ApplicationFiled: November 13, 2001Publication date: May 15, 2003Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITEDInventors: Siew Yong Kong, Alex See, Simon Chooi, Gautam Sarkar
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Publication number: 20030075766Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.Type: ApplicationFiled: August 26, 2002Publication date: April 24, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
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Publication number: 20030069151Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.Type: ApplicationFiled: October 9, 2001Publication date: April 10, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Jianhui Ye, Simon Chooi, Alex See
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Patent number: 6540841Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: GrantFiled: June 30, 2000Date of Patent: April 1, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6534388Abstract: A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.Type: GrantFiled: September 27, 2000Date of Patent: March 18, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wenhe Lin, Zhong Dong, Simon Chooi, Kin Leong Pey
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Patent number: 6530380Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.Type: GrantFiled: November 19, 1999Date of Patent: March 11, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Mei Sheng Zhou, Vincent Sih, Simon Chooi, Zainab Bte Ismail, Ping Yu Ee, Sang Yee Loong
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Patent number: 6531390Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.Type: GrantFiled: August 10, 2001Date of Patent: March 11, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
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Patent number: 6531386Abstract: A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed.Type: GrantFiled: February 8, 2002Date of Patent: March 11, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Victor Seng-Keong Lim, Simon Chooi, Randall Cha