Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract: A downward or vertical flow-through rapid diagnostic device and assay are provided. The device comprises a test area and reagent storage area, which are linked via a channel. The test area further comprises a reaction zone and an absorbent zone. A capture reagent is immobilized on the reaction zone to detect a target analyte in the fluid test sample. The fluid test sample flows downward or vertically through the reaction zone and into the absorbent zone, with the capture reagent and target analyte forming a two-membered complex that is concentrated in the reaction zone. The reagent storage area comprises a cartridge positioned vertically above the test area and a channel. A reagent used in the assay is housed in the cartridge. Once liberated, the reagent passes through the channel and flows to test area for depositing on the reaction zone. The storage of predetermined amounts of reagents in the diagnostic device reduces the number of manual operations required to produce a result.

Abstract: A package for a chemical sensor including an encapsulation and a pressure balancing structure is disclosed. The encapsulation encapsulates a chemical sensor and has a hole for exposing a chemical sensitive part of the chemical sensor. The pressure balancing structure balances pressure applied to the chemical sensor at the chemical sensitive part.

Abstract: A downward or vertical flow-through rapid diagnostic device and assay are provided. The device comprises a test area and reagent storage area, which are linked via a channel. The test area further comprises a reaction zone and an absorbent zone. A capture reagent is immobilized on the reaction zone to detect a target analyte in the fluid test sample. The fluid test sample flows downward or vertically through the reaction zone and into the absorbent zone, with the capture reagent and target analyte forming a two-membered complex that is concentrated in the reaction zone. The reagent storage area comprises a breakable cartridge positioned directly and vertically above the test area and a channel. A reagent used in the assay is housed in the breakable cartridge. Once liberated, the reagent passes through the channel and flows to test area for depositing on the reaction zone.

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices.

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract: A passive anti-arcing protection components for electronic ballasts of fluorescent lamps. This protection component is a bridge-rectifier-resistor-capacitor network, containing at least a diode, a resistor, and a capacitor. The component's circuitry is electrically connected to the ballast at the lamp side, acting as a low-resistance redirection path for any sudden change in energy. When an arcing condition is about to occur, this protection circuitry absorbs the spark energy, ceasing the arcing condition.

Abstract: A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

Abstract: An electronic circuit for driving an LED device, including an LED, a driver for supply current to the LED array, and one or two current detection modules connected to one or both ends of the LED array for detecting current level and sending signals about the current level detected to the driver, which will break the circuit immediately upon detecting a fault condition on either side of the LED array based on the feedback from one or both current detection modules.

Abstract: A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

Abstract: A passive anti-arcing protection components for electronic ballasts of fluorescent lamps. This protection component is a bridge-rectifier-resistor-capacitor network, containing at least a diode, a resistor, and a capacitor. The component's circuitry is electrically connected to the ballast at the lamp side, acting as a low-resistance redirection path for any sudden change in energy. When an arcing condition is about to occur, this protection circuitry absorbs the spark energy, ceasing the arcing condition.

Abstract: An electronic circuit for driving an LED device, including an LED, a driver for supply current to the LED array, and one or two current detection modules connected to one or both ends of the LED array for detecting current level and sending signals about the current level detected to the driver, which will break the circuit immediately upon detecting a fault condition on either side of the LED array based on the feedback from one or both current detection modules.

Abstract: A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

Abstract: A downward or vertical flow-through rapid diagnostic device and assay are provided. The device comprises a test area and reagent storage area, which are linked via a channel. The test area further comprises a reaction zone and an absorbent zone. A capture reagent is immobilized on the reaction zone to detect a target analyte in the fluid test sample. The fluid test sample flows downward or vertically through the reaction zone and into the absorbent zone, with the capture reagent and target analyte forming a two-membered complex that is concentrated in the reaction zone. The reagent storage area comprises a breakable cartridge positioned directly and vertically above the test area and a channel. A reagent used in the assay is housed in the breakable cartridge. Once liberated, the reagent passes through the channel and flows to test area for depositing on the reaction zone.

Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A ballast circuit for controlling preheating, ignition or performing dimming of a gas discharge lamp such as a compact fluorescent lamp is disclosed. The ballast circuit has an inverter connected to a pair of input terminals for receiving a supply voltage, a base drive transformer connected to the switching transistor inverter to provide a drive signal, a resonant circuit connected to the switching transistor inverter, and a loading circuit connected to the base drive transformer. The base drive transformer includes a primary winding and a secondary winding set. The loading circuit is adapted for at least temporarily saturating the base drive transformer and thus effecting in the resonant circuit an oscillating frequency different from a natural resonant frequency of the resonant circuit.