Patents by Inventor Sing Chan
Sing Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7670915Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.Type: GrantFiled: March 1, 2004Date of Patent: March 2, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Errol Todd Ryan, Paul R. Besser, Simon Siu-Sing Chan, Robert J. Chiu, Mehrdad Mahanpour, Minh Van Ngo
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Publication number: 20090032888Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: William G. En, Thorsten Kammler, Eric N. Paton, Paul R. Besser, Simon Siu-Sing Chan
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Publication number: 20090008402Abstract: The present invention relates to a hygienic rubbish capable of killing harmful bacteria and expelling odors that may result from rubbish. The hygienic bin accomplishes this by including as components an ultraviolet light and exhaust system.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Applicant: The Hong Kong Polytechnic UniversityInventors: Alan Kin-tak Lau, Kwan Sing Chan, Chi Pang Leung, Ching Man Yu
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Patent number: 7456062Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.Type: GrantFiled: August 23, 2005Date of Patent: November 25, 2008Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Thorsten Kammler, Eric N. Paton, Paul R. Besser, Simon Siu-Sing Chan
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Publication number: 20080150011Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Simon Siu-Sing Chan, Lei Xue, YouSeok Suh, Amol Ramesh Joshi, Hidehiko Shiraiwa, Harpreet Sachar, Kuo-Tung Chang, Connie Pin Chin Wang, Paul R. Besser, Shenqing Fang, Meng Ding, Takashi Orimoto, Wei Zheng, Fred TK Cheung
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Publication number: 20080149990Abstract: A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.Type: ApplicationFiled: April 13, 2007Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Connie Pin Chin Wang, Paul R. Besser, Simon Siu-Sing Chan, YouSeok Suh, Shenqing Fang
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Publication number: 20080150042Abstract: A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.Type: ApplicationFiled: December 17, 2007Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Simon Siu-Sing Chan, Hidehiko Shiraiwa, Kuo-Tung Chang, Angela T. Hui
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Publication number: 20080153224Abstract: An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.Type: ApplicationFiled: April 13, 2007Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Connie Pin Chin Wang, Simon Siu-Sing Chan, Angela T. Hui, Paul R. Besser, Shenqing Fang
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Publication number: 20080142874Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.Type: ApplicationFiled: December 16, 2006Publication date: June 19, 2008Applicants: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Hidehiko Shiraiwa, Takayuki Maruyama, Kuo-Tung Chang, YouSeok Suh, Amol Ramesh Joshi, Harpreet Sachar, Simon Siu-Sing Chan
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Publication number: 20080042588Abstract: A ballast circuit for controlling preheating, ignition or performing dimming of a gas discharge lamp such as a compact fluorescent lamp is disclosed. The ballast circuit has an inverter connected to a pair of input terminals for receiving a supply voltage, a base drive transformer connected to the switching transistor inverter to provide a drive signal, a resonant circuit connected to the switching transistor inverter, and a loading circuit connected to the base drive transformer. The base drive transformer includes a primary winding and a secondary winding set. The loading circuit is adapted for at least temporarily saturating the base drive transformer and thus effecting in the resonant circuit an oscillating frequency different from a natural resonant frequency of the resonant circuit.Type: ApplicationFiled: November 29, 2005Publication date: February 21, 2008Inventors: Cho Sing Chan, Ronald Bezdon
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Patent number: 7250667Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.Type: GrantFiled: January 5, 2006Date of Patent: July 31, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Darin A. Chan, Simon Siu-Sing Chan, Paul L. King
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Patent number: 7132352Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.Type: GrantFiled: August 6, 2004Date of Patent: November 7, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Simon Siu-Sing Chan, Paul R. Besser, Jeffrey P. Patton
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Patent number: 7064067Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.Type: GrantFiled: February 2, 2004Date of Patent: June 20, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Paul L. King, Simon Siu-Sing Chan, Jeffrey P. Patton, Minh Van Ngo
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Patent number: 7023059Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.Type: GrantFiled: March 1, 2004Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Darin A. Chan, Simon Siu-Sing Chan, Jeffrey P. Patton, Jacques J. Bertrand
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Patent number: 7015076Abstract: A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.Type: GrantFiled: March 1, 2004Date of Patent: March 21, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Darin A. Chan, Simon Siu-Sing Chan, Paul L. King
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Patent number: 7005357Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.Type: GrantFiled: January 12, 2004Date of Patent: February 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Simon Siu-Sing Chan, Paul R. Besser, Paul L. King, Errol Todd Ryan, Robert J. Chiu
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Patent number: 6969678Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.Type: GrantFiled: November 3, 2003Date of Patent: November 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan
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Patent number: 6964875Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.Type: GrantFiled: October 13, 2004Date of Patent: November 15, 2005Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Mark W. Michael, Hai Hong Wang, Simon Siu-Sing Chan
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Patent number: 6841832Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.Type: GrantFiled: December 19, 2001Date of Patent: January 11, 2005Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Mark W. Michael, Hai Hong Wang, Simon Siu-Sing Chan
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Publication number: 20040150373Abstract: The subject invention is about a portable battery jump starting device for stranded vehicle due to weaken starting battery. It is equipped with a pair of power cable connected to crocodile clips. The internal circuit of the subject invention is capable of detecting polarity at the point of connection to the external battery and is capable of compensating a wrong polarity connection. The subject invention offers automatic power on/off and a will guarantee a correction connection at any circumstance. Therefore it eliminates the risk of battery explosion due to human error.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventor: Sing Chan