Patents by Inventor Sipeng Gu

Sipeng Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111264
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Jiehui SHU, Sipeng GU, Haiting WANG
  • Publication number: 20210111261
    Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Inventors: JIEHUI SHU, JUDSON ROBERT HOLT, SIPENG GU, HAITING WANG
  • Patent number: 10937685
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sipeng Gu, Haiting Wang, Jiehui Shu
  • Publication number: 20210050419
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 18, 2021
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
  • Publication number: 20210043766
    Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Baofu Zhu, Shesh Mani Pandey, Jiehui Shu, Sipeng Gu, Haiting Wang
  • Publication number: 20200411684
    Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which comprise an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure comprises a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Jiehui Shu, Judson R. Holt, Sipeng Gu, Haiting Wang
  • Publication number: 20200402838
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: SIPENG GU, HAITING WANG, JIEHUI SHU
  • Publication number: 20200388693
    Abstract: A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 10, 2020
    Inventors: SIPENG GU, ZHIGUO SUN, GUOLIANG ZHU, XINYUAN DOU
  • Publication number: 20200388540
    Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: SIPENG GU, JIEHUI SHU, HAITING WANG
  • Publication number: 20200373410
    Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.
    Type: Application
    Filed: May 26, 2019
    Publication date: November 26, 2020
    Inventors: TUNG-HSING LEE, SIPENG GU, JIEHUI SHU, HAITING WANG, ALI RAZAVIEH, WENJUN LI, KAVYA SREE DUGGIMPUDI, TAMILMANI ETHIRAJAN, BRADLEY MORGENFELD, DAVID NOEL POWER
  • Patent number: 10832839
    Abstract: Device structures and fabrication methods for an on-chip resistor. A dielectric layer includes a trench with a bottom and a sidewall arranged to surround the bottom. A metal layer is disposed on the dielectric layer at the sidewall of the trench. The metal layer includes a surface that terminates the metal layer at the bottom of the trench to define a discontinuity that extends along a length of the trench.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Scott Beasor, Haiting Wang, Sipeng Gu, Jiehui Shu
  • Patent number: 10833067
    Abstract: A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Scott H. Beasor, Zhenyu Hu
  • Patent number: 10825811
    Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaoming Yang, Sipeng Gu, Jeffrey Chee, Keith H. Tabakman
  • Patent number: 10818557
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Publication number: 20200266286
    Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 20, 2020
    Inventors: Xiaoming Yang, Sipeng Gu, Jeffrey Chee, Keith H. Tabakman
  • Patent number: 10714380
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sipeng Gu, Sunil K. Singh, Xinyuan Dou, Akshey Sehgal, Zhiguo Sun
  • Publication number: 20200135545
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Ravi P. SRIVASTAVA, Sipeng GU, Sunil K. SINGH, Xinyuan DOU, Akshey SEHGAL, Zhiguo SUN
  • Patent number: 10580857
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Yanzhen Wang, Xinyuan Dou, Hongliang Shen, Sipeng Gu
  • Publication number: 20200013678
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Publication number: 20190386100
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Inventors: Yanzhen Wang, Xinyuan Dou, Hongliang Shen, Sipeng Gu