Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). An example DRAM device may include a plurality of pillars extending from a base of a substrate, a gate formed around the plurality of pillars, and a buried bitline formed within the base, wherein an upper surface of the buried bitline is recessed below an upper surface of the base. The DRAM device may further include a bottom source/drain formed beneath the plurality of pillars, and a contact formed in the bottom source/drain, between the plurality of pillars.

Abstract: Disclosed are approaches for forming 4F2 vertical DRAM devices including buried bitlines. One DRAM device may include a plurality of bitlines between a plurality of vertical structures extending from a substrate, and a bottom source/drain formed in each of the plurality of vertical structures in a saddle area, wherein the saddle area comprises a saddle trench formed through the plurality of vertical structures. The DRAM device may further include a dielectric film formed over the plurality of vertical structures in the saddle area, wherein the dielectric film is present along a portion of the plurality of bitlines and along just a first sidewall the plurality of vertical structures in the saddle area, and a fill material over the plurality of vertical structures of the saddle area, wherein the fill material directly contacts the plurality of bitlines.

Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). In one approach, a method may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants, and annealing the plurality of bridge layers. The method may further include forming a contact by directing second ions into an upper surface of the plurality of bridge layers while the substrate is at the low temperature, and forming a pillar over the contact.

Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source/drain formed in the base layer and a top source/drain formed in each pillar of the plurality of pillars, wherein the top source/drain extends above the gate.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.

Abstract: Disclosed herein are approaches for forming dynamic DRAM devices without trench fill voids. A method may include providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures, and depositing a plurality of layers over the device structures. The layers may include a first layer over the device structures, a second layer over the first layer, and a third layer over the second layer. The method may further include forming a plurality of contact trenches through the plurality of layers to expose one or more device structures of the plurality of device structures, and directing ions into a sidewall of the trenches at a non-zero angle, wherein the ions impact the third layer without impacting the second layer. The method may further include forming a fill material within the trenches after the ions are directed into the sidewall of the trenches.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Disclosed herein are approaches for forming a SiC MOSFET including at least one trench with rounded corners. In one approach, a method may include providing a masking layer over a silicon carbide (SiC) layer, wherein an opening is formed in the masking layer, and providing a sidewall spacer along a sidewall of the opening of the masking layer. The method may further include forming an implant region within the SiC layer by directing ions through the opening defined by the sidewall spacer, performing a first etch to the SiC layer, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess, and performing a second etch to remove the set of shoulder regions.

Abstract: Disclosed herein are approaches for forming a FDSOI, single diffusion break device. In one approach, a method may include providing a plurality of gates in a stack of layers, wherein each gate of the plurality of gates comprises a sidewall spacer, and forming a mask over the stack of layers, wherein an opening through the mask exposes a dummy gate of the plurality of gates. The method may further comprise etching a gate material of the dummy gate to form a recess in a silicon-on-insulator (SOI) layer of the stack of layers, implanting oxygen ions into the recess, and annealing the SOI layer within the recess to form an isolation area.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

Abstract: A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

Abstract: A method of isolating sections of the channel layer in a SOI workpiece is disclosed. Rather than etching material to create trenches, which are then filled with a dielectric material, ions are implanted into portions of the channel layer to transform these implanted regions from silicon or silicon germanium into an electrically insulating material. These ions may comprise at least one isolating species, such as oxygen, nitrogen, carbon or boron. This eliminates various processes from the fabrication sequence, including an etching process and a deposition process. Advantageously, this approach also results in greater axial strain in the channel layer, since the channel layer is continuous across the workpiece.

Abstract: A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.