Patents by Inventor Sipeng Gu

Sipeng Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160099171
    Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.
    Type: Application
    Filed: December 15, 2015
    Publication date: April 7, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang HU, Yuping REN, Duohui BEI, Sipeng GU, Huang LIU
  • Patent number: 9305832
    Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiang Hu, Yuping Ren, Duohui Bei, Sipeng Gu, Huang Liu
  • Patent number: 9281249
    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: March 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alok Vaid, Abner Bello, Sipeng Gu, Lokesh Subramany, Xiang Hu, Akshey Sehgal
  • Publication number: 20160005598
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng GU, Sandeep GAAN, Zhiguo SUN, Huang LIU, Adam SELSLEY
  • Publication number: 20150380246
    Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.
    Type: Application
    Filed: June 26, 2014
    Publication date: December 31, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xiang HU, Yuping REN, Duohui BEI, Sipeng GU, Huang LIU
  • Publication number: 20150348913
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Application
    Filed: August 4, 2015
    Publication date: December 3, 2015
    Applicant: Globalfoundries Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Publication number: 20150340296
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Application
    Filed: August 3, 2015
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Patent number: 9184288
    Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Zhiguo Sun, Sandeep Gaan, Danni Chen, Wen-Pin Peng, Huang Liu
  • Publication number: 20150287795
    Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Sandeep Gaan, Sipeng Gu
  • Publication number: 20150263169
    Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng GU, Zhiguo SUN, Sandeep GAAN, Danni CHEN, Wen-Pin PENG, Huang LIU
  • Patent number: 9129905
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 8, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Patent number: 9121890
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Publication number: 20150198435
    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Alok VAID, Abner BELLO, Sipeng GU, Lokesh SUBRAMANY, Xiang HU, Akshey SEHGAL
  • Publication number: 20150123212
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Publication number: 20150115267
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal