Patents by Inventor Sipeng Gu

Sipeng Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210399126
    Abstract: An illustrative transistor device disclosed herein includes a gate structure positioned around a portion of a fin defined in a semiconductor substrate and epitaxial semiconductor material positioned on the fin in a source/drain region of the transistor device, wherein the epitaxial semiconductor material has a plurality of lower angled surfaces. In this example, the device further includes a first sidewall spacer positioned adjacent the gate structure, wherein a first portion of the first sidewall spacer is also positioned on and in physical contact with at least a portion of the lower angled surfaces of the epitaxial semiconductor material.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Inventors: Sipeng Gu, Judson R. Holt, Haiting Wang, Yanping Shen
  • Publication number: 20210391323
    Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Yanping Shen, Haiting Wang, Sipeng Gu
  • Publication number: 20210391250
    Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. The present disclosure provides a semiconductor device including a first device region and a second device region. The first device region includes a first metal layer, a first via structure over the first metal layer, a second via structure over the first via structure, and a second metal layer over the second via structure. The first via structure and the second via structure electrically couple the second metal layer to the first metal layer. The second device region includes a third metal layer, a contact structure over the third metal layer, a memory cell structure over the contact structure, and a fourth metal layer over the memory cell structure. The first via structure and the contact structure are made of the same material.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: JUN LIAN, SIPENG GU, HAITING WANG, YANPING SHEN
  • Publication number: 20210376106
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 2, 2021
    Inventors: Jiehui SHU, Sipeng GU, Haiting WANG
  • Patent number: 11177385
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Baofu Zhu
  • Patent number: 11164954
    Abstract: A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Sipeng Gu, Zhiguo Sun, Guoliang Zhu, Xinyuan Dou
  • Patent number: 11164795
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sipeng Gu, Judson Holt, Haiting Wang, Bangun Indajang
  • Publication number: 20210336126
    Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Inventors: Yanping Shen, Haiting Wang, Sipeng Gu
  • Patent number: 11158633
    Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 26, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Haiting Wang, Sipeng Gu, Shesh Mani Pandey, Lixia Lei, Gregory Costrini
  • Publication number: 20210320207
    Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 14, 2021
    Inventors: Haiting Wang, Judson R. Holt, Sipeng Gu
  • Publication number: 20210320244
    Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Inventors: Sipeng Gu, Haiting Wang, Yanping Shen
  • Publication number: 20210320189
    Abstract: One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 14, 2021
    Inventors: Sipeng Gu, Haiting Wang
  • Publication number: 20210313321
    Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Haiting Wang, Sipeng Gu, Shesh Mani Pandey, Lixia Lei, Gregory Costrini
  • Publication number: 20210305103
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Sipeng Gu, Judson Holt, Haiting Wang, Bangun Indajang
  • Publication number: 20210305495
    Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: Yanping Shen, Haiting Wang, Sipeng Gu
  • Patent number: 11133417
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body, a second gate structure that extends over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is positioned laterally between the first section of the first semiconductor layer and the second section of the first semiconductor layer.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 28, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sipeng Gu, Judson Holt, Halting Wang
  • Patent number: 11127834
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 21, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC
    Inventors: Jiehui Shu, Sipeng Gu, Halting Wang
  • Publication number: 20210288182
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body, a second gate structure that extends over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is positioned laterally between the first section of the first semiconductor layer and the second section of the first semiconductor layer.
    Type: Application
    Filed: March 16, 2020
    Publication date: September 16, 2021
    Inventors: Sipeng Gu, Judson Holt, Haiting Wang
  • Patent number: 11114466
    Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 7, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Publication number: 20210249508
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu