Patents by Inventor Sipeng Gu

Sipeng Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190386100
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Inventors: Yanzhen Wang, Xinyuan Dou, Hongliang Shen, Sipeng Gu
  • Patent number: 10446483
    Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
  • Publication number: 20190221515
    Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.
    Type: Application
    Filed: January 16, 2018
    Publication date: July 18, 2019
    Inventors: Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
  • Patent number: 10347531
    Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xusheng Wu, Xinyuan Dou, Xiaobo Chen, Guoliang Zhu, Wenhe Lin, Jeffrey Chee
  • Patent number: 10347528
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Sipeng Gu, Akshey Sehgal
  • Publication number: 20190081155
    Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 14, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong XIE, Kangguo CHENG, Nicolas LOUBET, Xin MIAO, Pietro MONTANINI, John ZHANG, Haigou HUANG, Jianwei PENG, Sipeng GU, Hui ZANG, Yi QI, Xusheng WU
  • Patent number: 10211317
    Abstract: Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Xusheng Wu, Jianwei Peng, Sipeng Gu, Hsien-Ching Lo
  • Publication number: 20190051735
    Abstract: Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 14, 2019
    Inventors: Yi Qi, Xusheng Wu, Jianwei Peng, Sipeng Gu, Hsien-Ching Lo
  • Publication number: 20180358267
    Abstract: At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanzhen Wang, Xinyuan Dou, Sipeng Gu
  • Patent number: 10153211
    Abstract: At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanzhen Wang, Xinyuan Dou, Sipeng Gu
  • Patent number: 10121711
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Patent number: 10068810
    Abstract: A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins may be formed by etching an active epitaxial layer that is disposed over the substrate. An intervening sacrificial epitaxial layer may be used to template growth of the active epitaxial layer, and is then removed and backfilled with an isolation dielectric layer. The isolation dielectric layer may be disposed between bottom surfaces of the fins and the substrate, and may be deposited, for example, following the etching process used to define the fins. Within different regions of the substrate, dielectrically isolated fins of different heights may have substantially co-planar top surfaces.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Yi Qi, Jianwei Peng, Hsien-Ching Lo, Sipeng Gu
  • Publication number: 20180240703
    Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: SIPENG GU, XUSHENG WU, XINYUAN DOU, XIAOBO CHEN, GUOLIANG ZHU, WENHE LIN, JEFFREY CHEE
  • Publication number: 20180233566
    Abstract: Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 16, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: SIPENG GU, XUSHENG WU, WENHE LIN, JEFFREY CHEE
  • Publication number: 20180204920
    Abstract: Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.
    Type: Application
    Filed: January 19, 2017
    Publication date: July 19, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: SIPENG GU, XUSHENG WU, WENHE LIN, JEFFREY CHEE
  • Patent number: 10026818
    Abstract: Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xusheng Wu, Wenhe Lin, Jeffrey Chee
  • Patent number: 10014296
    Abstract: Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions that are within a semiconductor fin and that define the active device region(s) for the FINFET(s). The isolation regions are formed so that they include a semiconductor liner. The semiconductor liner ensures that, when a source/drain recess is formed immediately adjacent to the isolation region, the bottom and opposing sides of the source/drain recess will have semiconductor surfaces onto which epitaxial semiconductor material for a source/drain region is grown. As a result, the angle of the top surface of the source/drain region relative to the top surface of the semiconductor fin is minimized. Thus, the risk that a subsequently formed source/drain contact will not reach the source/drain region is also minimized. Also disclosed is a semiconductor structure formed according to the method.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xinyuan Dou, Hong Yu, Sipeng Gu, Yanzhen Wang
  • Patent number: 9666476
    Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Yuping Ren, Duohui Bei, Sipeng Gu, Huang Liu
  • Patent number: 9502232
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Huang Liu, Adam Selsley
  • Patent number: 9466701
    Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Sandeep Gaan, Sipeng Gu