Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.

Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which comprise an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure comprises a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

Abstract: A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.

Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.

Abstract: Device structures and fabrication methods for an on-chip resistor. A dielectric layer includes a trench with a bottom and a sidewall arranged to surround the bottom. A metal layer is disposed on the dielectric layer at the sidewall of the trench. The metal layer includes a surface that terminates the metal layer at the bottom of the trench to define a discontinuity that extends along a length of the trench.

Abstract: A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.

Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.