Abstract: A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and transferring the data, stored in the second latch, to a third latch of the page buffer, resetting the first and second latches, reading data stored in LSB and MSB pages of a second word line, and storing the read data in the first and second latches, and sequentially outputting the data stored in the first latch and the data stored in the third latch, resetting the third latch, and then transferring the data stored in the second latch to the third latch.

Abstract: In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern.

Abstract: The present invention provides an etching composition, comprising a silyl phosphate compound, phosphoric acid and deionized water, and a method for fabricating a semiconductor, which includes an etching process employing the etching composition. The etching composition of the invention shows a high etching selectivity for a nitride film with respect to an oxide film. Thus, when the etching composition of the present invention is used to remove a nitride film, the effective field oxide height (EEH) may be easily controlled by controlling the etch rate of the oxide film. In addition, the deterioration in electrical characteristics caused by damage to an oxide film or etching of the oxide film may be prevented, and particle generation may be prevented, thereby ensuring the stability and reliability of the etching process.

Abstract: A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

Abstract: In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.

Abstract: A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.

Abstract: A method of verifying a non-volatile memory device includes precharging a bit line to a high level through a sensing node by applying a first voltage to a bit line select transistor coupled between the bit line and the sensing node; applying a verifying voltage to a plurality of word lines; disconnecting the bit line from the sensing node; and coupling the bit line to the sensing node by applying a second voltage to the bit line select transistor so as to detect a level of the bit line, the second voltage being smaller than the first voltage, wherein, a difference between the first voltage and the second voltage in a verifying operation is higher than a difference between a first voltage and a second voltage that are used in a read operation.

Abstract: An image sensor includes: a plurality of image pixels providing a reset signal and a data signal; a signal providing apparatus generating a ramp signal, and sequentially providing the reset signal, the data signal, and the ramp signal; and an analog-to-digital converting apparatus converting the data signal into a digital signal by using a first timing at which the amplitude of the ramp signal is changed based on the amplitude of the reset signal and a second timing at which the amplitude of the ramp signal is changed based on the amplitude of the data signal, wherein the reset signal used to generate the ramp signal and the data signal which has been converted into the data digital signal may be output from the same image pixel.

Abstract: A phase-change memory device with an improved current characteristic is provided.

Abstract: A digital image processing apparatus and method are provided. The digital image processing apparatus includes: a Y component processing unit receiving a Y component and performing edge enhancement processing and first noise reduction processing on the Y component by using a memory allocated to the Y component; and a CbCr processing unit receiving a Cb component and a Cr component, and performing false color suppression processing and second noise reduction processing on the Cb component and the Cr component by using a memory allocated to the Cb component and the Cr component, where the Y component, the Cb component and the Cr component are variables of the YCbCr color space.

Abstract: A semiconductor device includes: a fuse pattern formed at a first level, a first line pattern formed at a second level lower than the first level, a second line pattern formed at a third level higher than the first level, a first contact plug coupling the fuse pattern to the first line pattern 310, a second contact plug coupling the fuse pattern to the second line pattern, and a fuse blowing region provided over first line pattern and overlapping with the first contact plug at least partially.

Abstract: A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signals, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes and extend laterally in opposite directions so as to define a zigzag arrangement together.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period.

Abstract: A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated.

Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.

Abstract: A variable resistor, a nonvolatile memory device and methods of fabricating the same are provided. The variable resistor includes an anode electrode and a cathode electrode, a variable resistive layer including CdS nanoscale particles provided between the anode electrode and the cathode electrode, and an initial metal atom diffusion layer within the variable resistive layer. The variable resistor is a bipolar switching element and configured to be in a reset state when a positive voltage relative to a cathode electrode is applied to the anode electrode, and configured to be in a set state when a negative voltage relative to the cathode electrode is applied to the anode electrode.

Abstract: A non-volatile memory device and a method of manufacturing the same are provided. A first portion stack having a first circuit element including at least one layer selected from at least one diode layer, at least one variable resistive layer, and interconnection layer is formed on a first substrate. A second portion stack having a second circuit element including at least the other layer selected from the at least one diode layer, the at least variable resistive layer, and the at least interconnection layer is formed on a second substrate. The first circuit element and the second circuit element are bonded together and the second substrate is removed.