Abstract: A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.

Abstract: An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit.

Abstract: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Abstract: A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address.

Abstract: A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

Abstract: A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

Abstract: An image data processing method includes generating a data window comprising N rows and N columns using Bayer data from a pixel array, generating a red (R), green (G), blue (B) data of a center pixel in the data window, detecting an edge region in the data window, detecting a bright region in the data window, adjusting the R, G, B data using a suppressing gain factor if both of the edge region and bright region is detected, and outputting the adjusting R, G, B data as a result of an interpolating process.

Abstract: A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor.

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

Abstract: A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command.

Abstract: A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.