Patents by Inventor Soichi Homma

Soichi Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210082856
    Abstract: A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventor: Soichi HOMMA
  • Patent number: 10943844
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Publication number: 20200185373
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 10600773
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Publication number: 20190393114
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Masatoshi KAWATO, Masayuki MIURA, Masatoshi FUKUDA, Soichi HOMMA
  • Patent number: 10354977
    Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Masatoshi Fukuda
  • Patent number: 10312197
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yuusuke Takano, Takashi Imoto, Takeshi Watanabe, Soichi Homma, Katsunori Shibuya
  • Publication number: 20180277515
    Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Soichi Homma, Masatoshi Fukuda
  • Publication number: 20180261574
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Application
    Filed: September 3, 2017
    Publication date: September 13, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
  • Patent number: 9960143
    Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 1, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Naoyuki Komuta
  • Publication number: 20180076187
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 15, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 9881876
    Abstract: A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Yuusuke Takano
  • Patent number: 9824905
    Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
  • Publication number: 20170263585
    Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.
    Type: Application
    Filed: September 1, 2016
    Publication date: September 14, 2017
    Inventors: Soichi HOMMA, Naoyuki KOMUTA
  • Patent number: 9646908
    Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 9, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masaya Shima, Yuusuke Takano, Takeshi Watanabe, Katsunori Shibuya
  • Publication number: 20170033086
    Abstract: A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 2, 2017
    Inventors: Soichi HOMMA, Yuusuke TAKANO
  • Publication number: 20170025321
    Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 26, 2017
    Inventors: Soichi HOMMA, Masaya SHIMA, Yuusuke TAKANO, Takeshi WATANABE, Katsunori SHIBUYA
  • Patent number: 9458535
    Abstract: A semiconductor manufacturing device has a conveyor configured to convey a tray having an unshielded semiconductor device mounted thereon to go through electromagnetic shielding, and a controller configured to control the conveyor. The controller performs control to take out the tray from a tray supply storage storing trays each having an unshielded semiconductor device mounted thereon to go through the electromagnetic shielding, place the tray on a carrier, and convey this carrier to a sputtering device which coats the unshielded semiconductor device with a sputtering material for the electromagnetic shielding, and the controller performs control to take out, from the sputtering device, the carrier having the tray placed thereon with an electromagnetically shielded semiconductor device being mounted on the tray, convey the tray, pick up the tray having the electromagnetically shielded semiconductor device mounted thereon from the carrier, and store the tray in the tray supply storage.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 4, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano