Patents by Inventor Soichi Homma

Soichi Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929332
    Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: March 12, 2024
    Assignee: Kioxia Corporation
    Inventors: Soichi Homma, Tatsuo Migita, Masayuki Miura, Takeori Maeda, Kazuhiro Kato, Susumu Yamamoto
  • Publication number: 20230307419
    Abstract: A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface.
    Type: Application
    Filed: August 23, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Soichi HOMMA, Chikara MIYAZAKI
  • Publication number: 20230307422
    Abstract: According to one or more embodiments, a semiconductor device includes a support having a recess. A plurality of semiconductor chips are stacked on each other in the recess. A plurality of columnar electrodes in the recess extend from the semiconductor chips toward an opening of the support. A wiring layer is disposed over the opening. The recess is filled with an insulating material to cover the semiconductor chips and the columnar electrodes.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Inventors: Takeori MAEDA, Soichi HOMMA
  • Patent number: 11705436
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: July 18, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Takeori Maeda, Yuusuke Takano, Soichi Homma
  • Publication number: 20230089223
    Abstract: A semiconductor device includes: an interconnect substrate including a plurality of interconnect layers; a first semiconductor chip disposed over the interconnect substrate; a second semiconductor chip disposed over the first semiconductor chip in a shifted manner and including a plurality of metal bumps on a surface of the second semiconductor chip facing the interconnect substrate; and a plurality of columnar electrodes connecting the interconnect structure to the metal bumps.
    Type: Application
    Filed: February 25, 2022
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Soichi HOMMA, Kazuma HASEGAWA
  • Publication number: 20230005879
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Inventor: Soichi HOMMA
  • Patent number: 11502057
    Abstract: A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 15, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Soichi Homma
  • Patent number: 11476230
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 18, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Soichi Homma
  • Publication number: 20220216184
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Applicant: Kioxia Corporation
    Inventors: Takeori MAEDA, Yuusuke TAKANO, Soichi HOMMA
  • Publication number: 20220199580
    Abstract: A semiconductor device according to the present embodiment includes a plurality of stacked first semiconductor chips. First columnar electrodes are connected to electrode pads of the first semiconductor chips and extend in a stacking direction of the first semiconductor chips. A plurality of second semiconductor chips are stacked above the first semiconductor chips. Second columnar electrodes are connected to electrode pads of the second semiconductor chips and extend in a stacking direction of the second semiconductor chips. Third columnar electrodes are respectively connected to tops of the first columnar electrodes and extend in the stacking direction of the second semiconductor chips. A resin layer covers the first semiconductor chips, the second semiconductor chips, the second columnar electrodes, and the third columnar electrodes and exposes tops of the second and third columnar electrodes.
    Type: Application
    Filed: August 26, 2021
    Publication date: June 23, 2022
    Applicant: Kioxia Corporation
    Inventors: Soichi HOMMA, Daisuke SAKAGUCHI
  • Patent number: 11302675
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Takeori Maeda, Yuusuke Takano, Soichi Homma
  • Publication number: 20220020722
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.
    Type: Application
    Filed: March 1, 2021
    Publication date: January 20, 2022
    Inventor: Soichi HOMMA
  • Publication number: 20220013477
    Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.
    Type: Application
    Filed: March 2, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Soichi HOMMA, Tatsuo MIGITA, Masayuki MIURA, Takeori MAEDA, Kazuhiro KATO, Susumu YAMAMOTO
  • Publication number: 20210398946
    Abstract: According to one or more embodiments, a semiconductor device includes a support having a recess. A plurality of semiconductor chips are stacked on each other in the recess. A plurality of columnar electrodes in the recess extend from the semiconductor chips toward an opening of the support. A wiring layer is disposed over the opening. The recess is filled with an insulating material to cover the semiconductor chips and the columnar electrodes.
    Type: Application
    Filed: February 26, 2021
    Publication date: December 23, 2021
    Inventors: Takeori MAEDA, Soichi HOMMA
  • Publication number: 20210257336
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Application
    Filed: August 31, 2020
    Publication date: August 19, 2021
    Applicant: Kioxia Corporation
    Inventors: Takeori MAEDA, Yuusuke TAKANO, Soichi HOMMA
  • Publication number: 20210257332
    Abstract: A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.
    Type: Application
    Filed: August 27, 2020
    Publication date: August 19, 2021
    Inventor: Soichi HOMMA
  • Publication number: 20210082856
    Abstract: A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventor: Soichi HOMMA
  • Patent number: 10943844
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama