Patents by Inventor Soichi Homma
Soichi Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200185373Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
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Patent number: 10600773Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: GrantFiled: March 1, 2017Date of Patent: March 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
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Publication number: 20190393114Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.Type: ApplicationFiled: February 5, 2019Publication date: December 26, 2019Applicant: Toshiba Memory CorporationInventors: Satoshi TSUKIYAMA, Hideo AOKI, Masatoshi KAWATO, Masayuki MIURA, Masatoshi FUKUDA, Soichi HOMMA
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Patent number: 10354977Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.Type: GrantFiled: September 12, 2017Date of Patent: July 16, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Soichi Homma, Masatoshi Fukuda
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Patent number: 10312197Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.Type: GrantFiled: September 2, 2014Date of Patent: June 4, 2019Assignee: Toshiba Memory CorporationInventors: Yuusuke Takano, Takashi Imoto, Takeshi Watanabe, Soichi Homma, Katsunori Shibuya
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Publication number: 20180277515Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventors: Soichi Homma, Masatoshi Fukuda
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Publication number: 20180261574Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.Type: ApplicationFiled: September 3, 2017Publication date: September 13, 2018Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
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Patent number: 9960143Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.Type: GrantFiled: September 1, 2016Date of Patent: May 1, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Soichi Homma, Naoyuki Komuta
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Publication number: 20180076187Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: ApplicationFiled: March 1, 2017Publication date: March 15, 2018Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
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Patent number: 9881876Abstract: A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer.Type: GrantFiled: July 29, 2016Date of Patent: January 30, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Soichi Homma, Yuusuke Takano
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Patent number: 9824905Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.Type: GrantFiled: September 10, 2014Date of Patent: November 21, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Publication number: 20170263585Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.Type: ApplicationFiled: September 1, 2016Publication date: September 14, 2017Inventors: Soichi HOMMA, Naoyuki KOMUTA
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Patent number: 9646908Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.Type: GrantFiled: July 22, 2016Date of Patent: May 9, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Homma, Masaya Shima, Yuusuke Takano, Takeshi Watanabe, Katsunori Shibuya
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Publication number: 20170033086Abstract: A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer.Type: ApplicationFiled: July 29, 2016Publication date: February 2, 2017Inventors: Soichi HOMMA, Yuusuke TAKANO
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Publication number: 20170025321Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.Type: ApplicationFiled: July 22, 2016Publication date: January 26, 2017Inventors: Soichi HOMMA, Masaya SHIMA, Yuusuke TAKANO, Takeshi WATANABE, Katsunori SHIBUYA
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Patent number: 9458535Abstract: A semiconductor manufacturing device has a conveyor configured to convey a tray having an unshielded semiconductor device mounted thereon to go through electromagnetic shielding, and a controller configured to control the conveyor. The controller performs control to take out the tray from a tray supply storage storing trays each having an unshielded semiconductor device mounted thereon to go through the electromagnetic shielding, place the tray on a carrier, and convey this carrier to a sputtering device which coats the unshielded semiconductor device with a sputtering material for the electromagnetic shielding, and the controller performs control to take out, from the sputtering device, the carrier having the tray placed thereon with an electromagnetically shielded semiconductor device being mounted on the tray, convey the tray, pick up the tray having the electromagnetically shielded semiconductor device mounted thereon from the carrier, and store the tray in the tray supply storage.Type: GrantFiled: September 10, 2014Date of Patent: October 4, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Patent number: 9385090Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.Type: GrantFiled: September 2, 2014Date of Patent: July 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Patent number: 9349694Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.Type: GrantFiled: August 29, 2014Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Katsunori Shibuya, Soichi Homma, Yuusuke Takano, Shinpei Ishida
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Patent number: 9236329Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.Type: GrantFiled: March 5, 2013Date of Patent: January 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Soichi Homma, Katsuyoshi Watanabe, Taku Nishiyama, Takeshi Ikuta, Naohisa Okumura
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Publication number: 20150170988Abstract: According to one embodiment, a plurality of semiconductor devices is mounted on a wiring substrate. A surface, on which a semiconductor devices of the wiring substrate are mounted, and the plurality of semiconductor devices are sealed by using a sealing resin. The wiring substrate which is sealed is cut and thus separated into semiconductor apparatuses. The semiconductor apparatuses after the separation are heated. A shield layer is formed by metal sputtering over wiring exposed at the edge of the cut wiring substrate and the sealing resin of the semiconductor apparatus, after the heating.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Takeshi WATANABE, Takashi IMOTO, Yuusuke TAKANO, Soichi HOMMA, Katsunori SHIBUYA