Patents by Inventor Soo Chung

Soo Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ECO-FRIENDLY FOAMING SHEET
    Publication number: 20130266767
    Abstract: The present invention provides an eco-friendly foaming sheet. More particularly, the eco-friendly foaming sheet is fabricated using a biodegradable resin composition on a substrate, wherein the biodegradable resin composition is applied to the substrate sheet, a print layer is formed thereon, and the treated sheet is subjected to foaming. According to the present invention, without processes of preparing a sheet and foaming using a biodegradable resin, the biodegradable resin layer is directly applied to a substrate sheet as a subject to be used and foamed while forming a print layer, in addition, a chemical foaming agent and an eco-friendly plasticizer used together with the biodegradable resin are specifically defined to ensure desired flexibility, thereby fabricating an eco-friendly foaming sheet with high productivity.
    Type: Application
    Filed: December 23, 2011
    Publication date: October 10, 2013
    Applicant: LG Hausys, Ltd.
    Inventors: Gun Soo Chung, Youn Woo Nam, Si Young Lee
  • CONNECTOR FOR DIGITAL BAND
    Publication number: 20130267111
    Abstract: Disclosed is a connector for a digital band, which is attached to the digital band and is quickly and easily attachable to an external circuit. The connector for a digital band includes a body portion having one end attached to the digital band, and at least one conductive portion connected to the digital yarn, and an insertion portion attached to the other end of the body portion and having at least one land connected to the conductive portion and exposed to the outside.
    Type: Application
    Filed: December 30, 2010
    Publication date: October 10, 2013
    Applicant: Korea Institute of Industrial Technology
    Inventors: Gi Soo Chung, Hyun Sub Park
  • Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages
    Publication number: 20130264720
    Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.
    Type: Application
    Filed: January 4, 2013
    Publication date: October 10, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-ho Chun, Byung-lyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
  • INTER CONNECTION STRUCTURE INCLUDING COPPER PAD AND PAD BARRIER LAYER, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME
    Publication number: 20130244419
    Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.
    Type: Application
    Filed: May 2, 2013
    Publication date: September 19, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo SHIN, Hyun-Soo CHUNG, Eun-Chul AHN, Jum-Gon KIM, Jin-Ho CHUN
  • VIA CONNECTION STRUCTURES, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS OF FABRICATING THE STRUCTURES AND DEVICES
    Publication number: 20130200525
    Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.
    Type: Application
    Filed: December 18, 2012
    Publication date: August 8, 2013
    Inventors: Ho-Jin LEE, Pil-Kyu KANG, Kyu-Ha LEE, Byung-Lyul PARK, Hyun-Soo CHUNG, Gil-Heyun CHOI
  • Wafer-level stack package and method of fabricating the same
    Patent number: 8482129
    Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Young Lee, Ho-Jin Lee, Hyun-Soo Chung, Ju-Il Choi, Son-Kwan Hwang
  • APPARATUS AND METHOD FOR CYBER-ATTACK PREVENTION
    Publication number: 20130167219
    Abstract: Provided are a method of preventing cyber-attack based on a terminal and a terminal apparatus therefor. The terminal apparatus includes: a packet processor configured to determine whether excessive traffic is generated by a transmission packet; an anomalous traffic detecting unit configured to determine whether anomalous traffic is generated, using a first condition of the excessive traffic being maintained for a first time period and a second condition of a generation count of the same kind of transmission packets exceeding a predetermined threshold value for a second time period; and a traffic block request unit configured to generate a traffic block request signal for requesting blockage of the transmission packet according to the result of determining whether anomalous traffic is generated.
    Type: Application
    Filed: September 14, 2012
    Publication date: June 27, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Woo-Sug JUNG, Jong-Dae PARK, Byung-Ho YAE, Tae-Soo CHUNG, Sung-Kee NOH, Sung-Jin MOON, Nam-Seok KO, Hwan-Jo HEO
  • Connector, receptable, and connector assembly for digital band
    Patent number: 8465316
    Abstract: Disclosed are a digital band connector, a receptacle, and a connector assembly for easily connecting digital bands formed of digital yarns to an external circuit. The digital band connector includes connect pins spaced apart from each other in a direction, passing through the digital bands made of digital yarns and to fix the digital bands, and electrically connected with the digital bands, a lower housing fixing the digital bands and the connect pins in a lower part and exposing one end of each of the connect pins through a lower surface, and an upper housing coupled with an upper part of the lower housing to fix the digital bands and the connect pins.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: June 18, 2013
    Assignee: Korea Institute of Industrial Technology
    Inventors: Gi Soo Chung, Dae Hoon Lee, Yeon Sang Kim, Jun Ho Park
  • Inter connection structure including copper pad and pad barrier layer, semiconductor device and electronic apparatus including the same
    Patent number: 8456012
    Abstract: A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: June 4, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Chang-Woo Shin, Hyun-Soo Chung, Eun-Chul Ahn, Jum-Gon Kim, Jin-Ho Chun
  • Semiconductor devices having redistribution structures and packages, and methods of forming the same
    Patent number: 8431479
    Abstract: Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: April 30, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Ki-Hyuk Kim, Nam-Seog Kim, Hyun-Soo Chung, Seok-Ho Kim, Myeong-Soon Park, Chang-Woo Shin
  • Wafer level package having a stress relief spacer and manufacturing method thereof
    Patent number: 8426252
    Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Ho-Jin Lee, Dong-Hyun Jang, Dong-Ho Lee
  • Methods for implementing variable speed scan testing
    Patent number: 8386866
    Abstract: In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: February 26, 2013
    Assignee: Eigenix
    Inventor: Sung Soo Chung
  • CONTACTLESSLY CHARGEABLE HEATER
    Publication number: 20130032589
    Abstract: The present invention relates to a contactlessly chargeable heater. In one example, the contactles sly chargeable heater includes: a charging patch emitting magnetic force by means of current applied to an inner coil; and a heating body, receiving the magnetic force from the charging patch to perform a contactless charging operation, and including a digital yarn for emitting heat via the power generated through the contactless charging operation. The digital yarn is woven together using threads within the heating body.
    Type: Application
    Filed: December 29, 2010
    Publication date: February 7, 2013
    Applicant: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventor: Gi Soo Chung
  • METHODS FOR OPERATING CONTROLLERS
    Publication number: 20130018934
    Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 17, 2013
    Inventors: Yong June Kim, Jung Soo Chung, Jun Jin Kong, Hongrak Son
  • Suppressor
    Publication number: 20130015942
    Abstract: This invention relates to a suppressor, including an element having sheets printed with a first internal electrode and a second internal electrode, and a discharge material disposed in a gap between the first internal electrode and the second internal electrode, wherein the discharge material is composed of a SiC—ZnO-based component, in which ZnO is reacted with the surface of SiC, thereby imparting much higher insulating properties and improving ESD resistance.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 17, 2013
    Applicant: AMOTECH CO., LTD.
    Inventors: Jun-Hwan JEONG, Seung-Chul LEE, Yeon-Soo CHUNG, Gug-Ho YOON
  • DEVICE AND METHOD FOR PROCESSING DATA
    Publication number: 20130007081
    Abstract: A data processing which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 3, 2013
    Inventors: KI JUN LEE, JUN JIN KONG, YONG JUNE KIM, JAE HONG KIM, HONG RAK SON, JUNG SOO CHUNG, SEONG HYEONG CHOI
  • SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES
    Publication number: 20120299194
    Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.
    Type: Application
    Filed: August 8, 2012
    Publication date: November 29, 2012
    Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
  • MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20120290783
    Abstract: A memory device including a randomizer and a memory system including the memory device are provided. The memory device includes: a randomizer including a sequence generator which generates a first sequence from a seed and a converter which converts the first sequence into a second sequence in response to a conversion factor, the randomizer randomizing data to be programmed using the second sequence and outputting the randomized data; and a storage area which receives the randomized data from the randomizer and storing the randomized data.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Soo CHUNG, Yong June KIM, Jun Jin KONG, Hongrak SON
  • WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF
    Publication number: 20120261821
    Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventors: Hyun-Soo Chung, Ho-Jin Lee, Dong-Hyun Jang, Dong-Ho Lee
  • Method and Apparatus for Fault Injection
    Publication number: 20120239993
    Abstract: The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Applicant: EIGENIX
    Inventor: Sung Soo Chung