Patents by Inventor Soo Chung

Soo Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170084558
    Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.
    Type: Application
    Filed: August 2, 2016
    Publication date: March 23, 2017
    Inventors: Sun-kyoung Seo, Tae-je Cho, Yong-hwan Kwon, Hyung-gil Baek, Hyun-soo Chung, Seung-kwan Ryu, Myeong-soon Park
  • Patent number: 9597366
    Abstract: The present invention relates to the anticancer composition containing an effective amount of herbal extract, and more particularly to the anticancer composition containing an effective amount of extract of Salviae Miltiorrhizae Radix, Chrysanthemum indicum, Acanthopanax senticosus, Cinnamomum cassia Blume, Eucommia ulmoides Oliv., Glycyrrhiza uralensis Fisch, Pueraria thunbergiana Benth, Crataegus pinnatifida Bunge, Cassia tora, Carthamus tinctorius L., Paeonia lactiflora Pall, and Angelica gigas Nakai. The anticancer composition containing an effective amount of herbal extract has advantage of minimal or few side effects and cytotoxicity as compared to many existing anticancer drugs having cytotoxicity and side effects.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 21, 2017
    Assignee: DONG-A UNIVERSITY RESEARCH FOUNDATION FOR INDUSTRY-ACADEMY COOPERATION
    Inventors: Jai-Heon Lee, Kyoung-Sook Kim, Young-Choon Lee, Chang-Woo Cho, KyoungMee Kim, Young Soo Chung
  • Publication number: 20170025384
    Abstract: Provided are a semiconductor chip and a semiconductor package capable of obtaining stability and reliability through a connection structure using a through-silicon-via (TSV). The semiconductor chip includes a semiconductor substrate and a through-silicon-via (TSV) structure penetrating through the semiconductor substrate. A connection pad includes a foundation base disposed on a lower surface of the semiconductor substrate and connected to the TSV structure. A protruding portion protrudes from the foundation base and extend to an inside of a first groove formed in a lower surface of the semiconductor substrate.
    Type: Application
    Filed: April 21, 2016
    Publication date: January 26, 2017
    Inventors: MYEONG-SOON PARK, HYUN-SOO CHUNG, CHAN-HO LEE
  • Publication number: 20170011976
    Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.
    Type: Application
    Filed: June 6, 2016
    Publication date: January 12, 2017
    Inventors: Myeong-soon PARK, Hyun-soo CHUNG, Chan-ho LEE
  • Publication number: 20160363522
    Abstract: A particulate matter sensor and an exhaust gas purification system using the same are provided. A particular matter sensor according to some embodiments of the present invention includes a first insulation layer including a first electrode unit exposed on a first side thereof, which includes a plurality of first electrodes not electrically connected to each other, a second insulation layer arranged in parallel to the first insulation layer with a space therebetween, including a second electrode unit on a first side thereof, which includes a plurality of second electrodes electrically connected to each other, a temperature sensing unit formed on a first side of a third insulation layer located on a second side of the second insulation layer, and a heater unit formed on a first side of a fourth insulation layer located on a second side of the third insulation layer, the heater unit configured to heat the first and second electrode units.
    Type: Application
    Filed: April 27, 2016
    Publication date: December 15, 2016
    Inventors: Yeon-Soo Chung, Soo-Min Oh, Eun-Ji Kim, Sung-Eun Jo, Yang-Joo Ko, Jung-Taek Kim, Heon-Joon Park, Tae-Kwan Yi
  • Publication number: 20160351472
    Abstract: An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure. A conductive pad is disposed on a second surface, opposite to the first surface, of the semiconductor structure. A through-substrate-via (TSV) structure penetrates through the semiconductor structure. An end portion of the TSV structure extends beyond the second surface of the semiconductor structure. The conductive pad surrounds the end portion of the TSV structure.
    Type: Application
    Filed: February 25, 2016
    Publication date: December 1, 2016
    Inventors: MYEONG-SOON PARK, HYUN-SOO CHUNG, CHAN-HO LEE
  • Patent number: 9495518
    Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong June Kim, Hong Rak Son, Jae Hong Kim, Sang Yong Yoon, Ki Jun Lee, Jung Soo Chung, Seong Hyeog Choi
  • Patent number: 9412707
    Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-soo Chung, Tae-je Cho, Jung-seok Ahn, In-young Lee
  • Patent number: 9403348
    Abstract: The present invention relates to sheets. The sheets include an adhesive layer, a base layer formed on the adhesive layer, a resin layer formed on the base layer, and a printed layer formed on the resin layer. Each of the adhesive layer and the resin layer includes a polylactic acid (PLA) resin. The sheets are biodegradable.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: August 2, 2016
    Assignee: LG HAUSYS, LTD.
    Inventors: Gun Soo Chung, Youn Woo Nam, Si Young Lee, Min Lee
  • Patent number: 9397377
    Abstract: A cavity filter is disclosed. The cavity filter includes: a housing in which at least one cavity is formed where the housing has a resonator held in the cavity; a cover joined to an upper portion of the housing; and a pressing member joined to the cover. An insertion area is formed in the cover for receiving the pressing member, where the insertion area includes a thin part that has a smaller thickness than the main body of the cover. The pressing member may be inserted in the insertion area to press the thin part. The pressing member includes an insert part that is inserted in the insertion area, and an elastic member that is joined to a lower portion of the insert part to press the thin part. The cavity filter can provide stable properties as the resonators are joined to the ground in a stable manner.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: July 19, 2016
    Assignee: ACE TECHNOLOGIES CORPORATION
    Inventors: Jae-Ok Seo, Sung-Soo Chung, Jung-Hak Ahn, Dong-Wan Chun, Kwang-Sun Park
  • Patent number: 9388581
    Abstract: The present invention relates to panels. The panels include a panel layer and a printed layer formed on the panel layer. The panel layer includes a polylactic acid (PLA) resin. The panels are environmentally friendly and biodegradable.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: July 12, 2016
    Assignee: LG HAUSYS, LTD.
    Inventors: Min Lee, Youn Woo Nam, Si Young Lee, Gun Soo Chung
  • Patent number: 9384087
    Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moshe Twitto, Avner Dor, Jun Jin Kong, Jung Soo Chung
  • Publication number: 20160188081
    Abstract: In touch panel display device, a first touch electrode group has a first plurality of touch electrodes and a second touch electrode group has a second plurality of touch electrodes. A first current supplier circuit supplies a first current during a first current supply period to the first touch electrode group, and the second current supplier circuit supplies a second current during a second current supply period to the second touch electrode group. The sensing signal receiver circuit holds a first touch voltage for the first touch electrode group following the first current supply period, and holds the second touch voltage for the second touch electrode group following the second current supply period. The sensing signal receiver determines based on the first held touch voltage and the second held touch voltage, whether a touch occurred in each of the first touch electrode group and the second touch electrode group.
    Type: Application
    Filed: May 29, 2015
    Publication date: June 30, 2016
    Inventors: Min Sung KIM, Hyung Uk JANG, Jin Soo CHUNG, Yoonion HWANG
  • Publication number: 20160189616
    Abstract: Disclosed is a method of driving a display device that includes, for example, generating a gate control signal, a data control signal and an image data using an image signal; generating a data voltage using the data control signal and the image data; generating a gate voltage using the gate control signal; and sequentially applying the gate voltage of a high level to q groups of the plurality of gate lines during q frames, respectively, where q is an integer greater than 1.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 30, 2016
    Inventors: Dae-Seok OH, Moon-Soo CHUNG
  • Patent number: 9378192
    Abstract: A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moshe Schwartz, Hong Rak Son, Jun Jin Kong, Jung Soo Chung
  • Patent number: 9365741
    Abstract: The present invention relates to sheets. The sheets include a base layer, a foamed layer formed on the base layer, a printed layer formed on the foamed layer, and a partially foamed layer formed on the printed layer. At least one layer of the foamed layer and the partially foamed layer includes a polylactic acid (PLA) resin. The sheets are biodegradable.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: June 14, 2016
    Assignee: LG HAUSYS, LTD.
    Inventors: Si Young Lee, Youn Woo Nam, Gun Soo Chung, Min Lee
  • Patent number: 9316691
    Abstract: The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: April 19, 2016
    Assignee: Eigenix
    Inventor: Sung Soo Chung
  • Patent number: 9268531
    Abstract: A nonvolatile memory device includes a data generating unit for generating a first reference value randomly or pseudo-randomly according to a first program request to program data in a memory cell, a seed selecting unit for selecting at least one of a plurality of seeds using the first reference value, and a randomizer for generating randomized data by using the selected seed. The data generating unit regenerates the first reference value as a second reference value different from the first reference value when a second program request is made, and the seed selecting unit selects another seed using the second reference value.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: February 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Hoon Woo, Hak-Sun Kim, Seong-Hyeog Choi, Jun-Jin Kong, Hong-Rak Son, Soon-Jae Won, Jung-Soo Chung
  • Publication number: 20150364432
    Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.
    Type: Application
    Filed: May 1, 2015
    Publication date: December 17, 2015
    Inventors: Hyun-soo CHUNG, Tae-je CHO, Jung-seok AHN, In-young LEE
  • Publication number: 20150363336
    Abstract: A method of operating a memory system including a first function block and a second function block includes generating a first authentication response indicating physical characteristics of the memory system, via the second function block, in response to a first authentication request received from the first function block; performing an error correction decoding on the first authentication response, via the first function block, by using first parity data corresponding to the first authentication request; and determining whether the second function block is authentic, depending on a result of the error correction decoding.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 17, 2015
    Inventors: SEONG-HYEOG CHOI, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon, Chang-Kyu Seol, Jung-Soo Chung