Patents by Inventor Soon-Cheon Seo

Soon-Cheon Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices with sidewall spacers of equal thickness
    Patent number: 10622259
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Soon-Cheon Seo
  • Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel
    Patent number: 10608114
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo
  • Vertical vacuum channel transistor with minimized air gap between tip and gate
    Patent number: 10600606
    Abstract: A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • BOOSTED VERTICAL FIELD-EFFECT TRANSISTOR
    Publication number: 20200091342
    Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.
    Type: Application
    Filed: December 4, 2019
    Publication date: March 19, 2020
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Vertical fin-type bipolar junction transistor with self-aligned base contact
    Patent number: 10593771
    Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Seyoung Kim, Injo Ok, Soon-Cheon Seo
  • Semiconductor devices with sidewall spacers of equal thickness
    Patent number: 10580704
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Soon-Cheon Seo
  • Reducing Off-State Leakage Current in Si/SiGe Dual Channel CMOS
    Publication number: 20200066600
    Abstract: Techniques for reducing off-state current in dual channel CMOS devices are provided. In one aspect, a method for forming a dual channel finFET includes: patterning NFET/PFET fins on a wafer from a first channel material and a second Ge-containing channel material; depositing a GeO2 layer on the fins; annealing the fins to selectively oxidize the at least one PFET fin; depositing a liner onto the fins which induces a negative charge in the PFET fin(s); removing unreacted GeO2 and the liner from the NFET fin(s); depositing a dielectric layer onto the fins which induces a positive charge in the NFET fin(s). A dual channel finFET device is also provided.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • REMOVAL OF TRILAYER RESIST WITHOUT DAMAGE TO UNDERLYING STRUCTURE
    Publication number: 20200066519
    Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS
    Publication number: 20200051866
    Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Nanosheet isolation for bulk CMOS non-planar devices
    Patent number: 10559654
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
  • Boosted vertical field-effect transistor
    Patent number: 10541329
    Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
    Publication number: 20200020598
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 16, 2020
    Inventors: Kangguo CHENG, Balasubramanian PRANATHARTHIHARAN, Soon-Cheon SEO
  • SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
    Publication number: 20200013682
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventors: Kangguo CHENG, Balasubramanian PRANATHARTHIHARAN, Soon-Cheon SEO
  • Techniques for Enhancing Vertical Gate-All-Around FET Performance
    Publication number: 20200006343
    Abstract: Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • PLANAR GATE-INSULATED VACUUM CHANNEL TRANSISTOR
    Publication number: 20190393012
    Abstract: A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Injo OK, Choonghyun LEE, Soon-Cheon SEO, Seyoung KIM
  • VERTICAL NANO-WIRE COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH CYLINDRICAL III-V COMPOUND AND GERMANIUM CHANNEL
    Publication number: 20190386145
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Injo OK, Choonghyun LEE, Soon-Cheon SEO
  • VERTICAL VACUUM CHANNEL TRANSISTOR WITH MINIMIZED AIR GAP BETWEEN TIP AND GATE
    Publication number: 20190378675
    Abstract: A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.
    Type: Application
    Filed: April 23, 2019
    Publication date: December 12, 2019
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • VERTICAL FIN-TYPE BIPOLAR JUNCTION TRANSISTOR WITH SELF-ALIGNED BASE CONTACT
    Publication number: 20190371900
    Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.
    Type: Application
    Filed: August 9, 2019
    Publication date: December 5, 2019
    Inventors: Choonghyun Lee, Seyoung Kim, Injo Ok, Soon-Cheon Seo
  • Minimize middle-of-line contact line shorts
    Patent number: 10490454
    Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Modified fin cut after epitaxial growth
    Patent number: 10475886
    Abstract: A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sivananda K. Kanakasabapathy, Fee Li Lie, Soon-Cheon Seo, Raghavasimhan Sreenivasan