Abstract: Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets.

Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins.

Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.

Abstract: A method of forming a bottom electrode for MRAM comprises: depositing a conductive material into a trench in a substrate and planarizing; depositing a selective cap on the conductive material; depositing a layer of high stress material on upper surfaces of the substrate and the cap; patterning the high stress material to remove the layer of high stress material on the upper surfaces of the substrate and leaving the layer of high stress material on the upper surfaces of the cap; depositing a layer of dielectric material on the upper surfaces of the substrate and on upper surfaces of the high stress material on the cap; planarizing the layer of dielectric material; and forming a magnetic tunnel junction stack on the dielectric material over the conductive material.

Abstract: Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

Abstract: A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: Techniques regarding a vertical transport complementary metal-oxide-semiconductor with a plurality of fin field effect transistors with varying threshold voltages are provided. For example, one or more embodiments can regard an apparatus, which can comprise a semiconductor substrate. The apparatus can also comprise a first conducting channel comprising a first concentration of a first element. The first conducting channel can extend from the semiconductor substrate, and the first element can be germanium. The apparatus can further comprise a second conducting channel comprising a second concentration of the first element. The second conducting channel can extend from the semiconductor substrate, and the first concentration can be greater than the second concentration. Moreover, the apparatus can comprise a metal dielectric gate adjacent to the first conducting channel and the second conducting channel.

Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode. A bottom dielectric layer is disposed on the first side of the bottom electrode around the gate structure. A top dielectric layer is disposed on the first side of the top electrode around the gate structure. A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode.

Abstract: A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.

Abstract: Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).

Abstract: A resistive processing unit includes an analog memory element coupled to a read row line and a read column line, a first current subtraction field-effect transistor (FET) coupled to the read row line and the analog memory element, and a second current subtraction FET coupled to the read column line and the analog memory element. The analog memory element is configured to store a weight value as its conductance. Application of a gate pulse voltage to one of the first current subtraction FET and the second current subtraction FET during application of a read pulse voltage to one of the read row line and the read column line reduces a measured conductance of the analog memory element, and the reduction of the measured conductance of the analog memory element provides net current for the stored weight value.

Abstract: A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.

Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.

Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

Abstract: A semiconductor structure includes a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.