Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

Abstract: A dual interlayer dielectric material structure is located on a passivation dielectric material liner and entirely fills a gap located between each memory device stack of a plurality of memory device stacks. The dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.

Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Abstract: A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

Abstract: Vertical transport field effect transistors (VTFET) are disclosed along with methods of making. The VTFET is made with a novel gate last replacement metal gate (RMG) process. The invention allows uniform and high doping levels without adversely affecting the gate region in the process. The distance from the S/D regions and the junctions are the same. Fin caps protect the fins and gate protecting hard mask protect the dummy gate material during the beginning process steps. The invention enables easy connection and increased surface area at the connection points to reduce contact resistance.

Abstract: A method of forming complementary metal-oxide-semiconductor (CMOS) nanosheet devices is provided. The method includes forming at least two adjacent trimmed stacks of sacrificial sheet segments and semiconductor nanosheet segments on a substrate, with a dummy gate structure and sidewall spacers on each of the at least two adjacent trimmed stacks. The method further includes forming a protective cap layer over the trimmed stacks, and forming a sacrificial fill layer on the protective cap layer. The method further includes forming a recess through the sacrificial fill layer and protective cap layer between the stacks, depositing a recess liner in the recess, and forming a dielectric fill layer in the recess on the recess liner. The method further includes forming a capping layer on one of the trimmed stacks, removing the sacrificial fill layer from another one of the trimmed stacks, and forming a source/drain on the semiconductor nanosheet segments.

Abstract: A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.

Abstract: A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.

Abstract: A vertical transport field effect transistor (VTFET) is provided that includes a vertical semiconductor channel material structure (i.e., fin or pillar) having a V-shaped groove located in the topmost surface thereof. A top source/drain structure is formed in contact with the V-shaped groove present in the topmost surface of the vertical semiconductor channel material structure. No drive-in anneal is needed to form the top source/drain structure. The presence of the V-shaped groove at the top junction region provides a VTFET that has improved device performance.

Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.

Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Abstract: A semiconductor structure is provided utilizing a cost effective method in which the vertical gate channel length is substantially the same for vertical field effect transistors (VFETs) that are present in a dense device region and an isolated device region. The VFETs have improved uniformity, device functionality and better yield. No additional lithographic process is used in making such a semiconductor structure.

Abstract: A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: A vertical transport field effect transistor (VTFET) is provided that includes a vertical semiconductor channel material structure (i.e., fin or pillar) having a V-shaped groove located in the topmost surface thereof. A top source/drain structure is formed in contact with the V-shaped groove present in the topmost surface of the vertical semiconductor channel material structure. No drive-in anneal is needed to form the top source/drain structure. The presence of the V-shaped groove at the top junction region provides a VTFET that has improved device performance.

Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

Abstract: A vertical transistor that includes a gate structure containing a work function metal liner that is wing-free is provided. The wing-free work function metal liner is provided by recessing a sacrificial material layer portion that is located adjacent to a work function metal liner having a winged surface near the channel and fin ends. The recessed sacrificial material layer portion allows for multi-directional etching of the winged surface of the work function metal liner and thus the wing surface can be removed forming a wing-free work function metal liner. The vertical transistor of the present application has reduced parasitic capacitance and a reduced tendency of electrical shorting between a top source/drain structure and the gate structure. The method of the present application can improve device yield.