Abstract: The embodiment disclosed herein is an actuator for camera comprising a lens module emitting light towards an image sensor; a housing enclosing the lens module; and a patterned member disposed on the internal surface of the housing wherein the internal surface is the one between the lens module and the image sensor. The patterned member comprises protrusions arranged in repetition along an optical axis, in which each protrusion extends lengthwise along a direction perpendicular to the optical axis.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a transparent substrate on the semiconductor chip, a dam structure between the semiconductor chip and the transparent substrate, a dummy pad on a lower side of the dam structure and to which no wiring is connected, a planarization film extending along an upper surface of the semiconductor chip and a passivation film on the planarization film, wherein the planarization film is spaced apart from the dam structure.

Abstract: The catalyst for methane reformation according to an exemplary embodiment of the present application consists of a porous metal support; and a perovskite-based catalyst component supported on the porous metal support and represented by Chemical Formula 1: Sr1-xAxTi1-yByO3-???[Chemical Formula 1] wherein all the variables are described herein.

Abstract: The present disclosure relates to a plurality of host materials and organic electroluminescent devices comprising the same. The present disclosure may provide a plurality of host materials having a composition favorable to thermal denaturation due to a low deposition temperature, while improving hole properties and electronic properties of HOMO and LUMO, by comprising separate compounds represented by formulas 1 and 2 into a light-emitting layer. By comprising the plurality of host materials of the present disclosure, it is possible to provide an organic electroluminescent device having a lower driving voltage, higher luminous efficiency and/or longer lifetime.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Abstract: A display device includes a first semiconductor layer disposed on a substrate; a first insulating layer disposed on the first semiconductor layer; a scan line disposed on the first insulating layer; a second insulating layer on the scan line; an inverted scan line on the second insulating layer; a third insulating layer disposed on the inverted scan line; a second semiconductor layer disposed on the third insulating layer; a fourth insulating layer disposed on the second semiconductor layer; an initializing voltage line disposed on the fourth insulating layer and overlapping the scan line; a first transistor including a channel disposed in the first semiconductor layer and receiving a gate signal through the scan line; and a second transistor including a channel disposed in the second semiconductor layer and receiving a gate signal through the inverted scan line.

Abstract: The catalyst for methane reformation according to an exemplary embodiment of the present application comprises: a porous metal support; perovskite-based catalyst particles supported on the porous metal support; and a perovskite-based binder supported on the porous metal support, and the perovskite-based catalyst particles and the perovskite-based binder each independently comprise the compound represented by Chemical Formula 1: Sr1-xAxTi1-yByO3-???[Chemical Formula 1] wherein all the variables are described herein.

Abstract: Disclosed are a relay method and device in a communication system. An operation method of a first communication node comprises the steps of: transmitting a reference signal to one or more candidate R nodes; receiving first feedback information including a minimum value of a first RSRP from a first candidate R node belonging to the one or more candidate R nodes; receiving second feedback information including a minimum value of a second RSRP from a second candidate R node belonging to the one or more candidate R nodes; comparing a first value based on the first feedback information with a second value based on the second feedback information; when the first value is greater than the second value, selecting the first candidate R node as an R node that is to perform a relaying operation; and communicating with a second communication node via the R node.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Abstract: A method of a transmitting terminal may include: setting an initial beam pairing flag indicating that the transmitting terminal transmitting sidelink-synchronization signal blocks (S-SSBs) is not a synchronization reference terminal; transmitting a plurality of S-SSBs including the initial beam pairing flag in a beam sweeping scheme; receiving, from a receiving terminal, information on a preferred beam among a plurality of beams through which the plurality of S-SSBs are transmitted; and transmitting data to the receiving terminal using the preferred beam.

Abstract: An operation method of a first terminal may include: transmitting a plurality of sidelink-synchronization signal blocks (S-SSBs); performing a monitoring operation on a plurality of response resources associated with the plurality of S-SSBs; receiving a first response signal from a second terminal in a first response resource among the plurality of response resources; identifying a first S-SSB associated with the first response resource among the plurality of S-SSBs; and determining a first transmission beam through which the first S-SSB is transmitted among a plurality of transmission beams of the first terminal as an optimal transmission beam.

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Abstract: Disclosed are a method and an apparatus for sidelink resource allocation in a wireless communication system. The method and apparatus for sidelink resource allocation in a wireless communication system, a method of a first terminal, may include: receiving, from a base station, resource pool configuration information including information on a resource sensing type; in response to that the information on the resource sensing type indicates a sensing operation, sensing transmission resource(s) within a sensing period according to the resource sensing type based on the scheduling information; selecting a first resource based on a result of the sensing on the transmission resource(s); and performing sidelink communication using the selected first resource.

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: An operation method of a relay node may include: receiving, from a first communication node, first data composed of n bits; receiving, from a second communication node, second data composed of m bits; in response to determining that n is greater than m, generating first T-data of m bits excluding (n?m) bits from the n-bits of the first data and first R-data of (n?m) bits; generating third data by performing a network coding operation on the first T-data and the second data; transmitting the third data to the first communication node; and transmitting the third data and the first R-data to the second communication node.

Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.