Patents by Inventor Soon-In Cho

Soon-In Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20170179025
    Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n?1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n?1)-th extended gate lines serves as a pad region, and the pad regions have different areas.
    Type: Application
    Filed: September 2, 2016
    Publication date: June 22, 2017
    Inventors: Seok-Jung YUN, Sung-Hun LEE, Jee-Hoon HAN, Yong-Won CHUNG, Seong Soon CHO
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    Publication number: 20170179028
    Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.
    Type: Application
    Filed: November 14, 2016
    Publication date: June 22, 2017
    Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
    Publication number: 20170110543
    Abstract: A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.
    Type: Application
    Filed: September 8, 2016
    Publication date: April 20, 2017
    Inventors: KYUNG-JUN SHIN, BYOUNGIL LEE, DONGSEOG EUN, HYUNKOOK LEE, SEONG SOON CHO
  • PAD STRUCTURES AND WIRING STRUCTURES IN A VERTICAL TYPE SEMICONDUCTOR DEVICE
    Publication number: 20170040254
    Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min HWANG, Young-Ho LEE, Seong-Soon CHO, Woon-Kyung LEE
  • Semiconductor device
    Patent number: 9553101
    Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taekyung Kim, Kwang Soo Seol, Hyunchul Back, Jin-Soo Lim, Seong Soon Cho
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170011992
    Abstract: A substrate structure may include a base substrate, a plurality of unit substrate regions arranged on the base substrate in one or more rows and one or more columns and spaced apart from one another, and dummy substrate regions between the unit substrate regions. In a row direction or a column direction, a first pitch between central points of two adjacent unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other.
    Type: Application
    Filed: June 12, 2016
    Publication date: January 12, 2017
    Inventors: Yu-duk KIM, Kyong-soon CHO, Shle-ge LEE, Da-hee PARK
  • WAFER LEVEL PACKAGE
    Publication number: 20160365319
    Abstract: A water level package includes a substrate, a plurality of semiconductor chips mounted on the substrate, and molding members that contact the substrate and the plurality of semiconductor chips and are formed on the substrate. The molding members include two or more molding members that have coefficients of thermal expansion (CTEs) different from each other.
    Type: Application
    Filed: January 21, 2016
    Publication date: December 15, 2016
    Inventors: Han-Sung RYU, Kyong-soon CHO
  • SEMICONDUCTOR DEVICES INCLUDING AUXILIARY BIT LINES
    Publication number: 20160343434
    Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: December 15, 2015
    Publication date: November 24, 2016
    Inventors: Joonhee Lee, Jiyoung Kim, Jintaek Park, Seong Soon Cho
  • Memory device
    Patent number: 9478560
    Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 25, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Soo Seol, JinTae Kang, Seong Soon Cho
  • Vertical type memory device
    Patent number: 9466613
    Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Seol, Seong-Soon Cho
  • SEMICONDUCTOR DEVICES INCLUDING INCREASED AREA CONTACTS
    Publication number: 20160284700
    Abstract: A semiconductor device can include a plurality of active patterns protruding from a substrate and spaced apart on the substrate by first and second distances. A plurality of selective epitaxial growth portions can be each grown on an upper surface of a respective one of the plurality of active patterns. A source/drain contact can be extending across the plurality of selective epitaxial growth portions to remain above top surfaces of first ones of plurality of active patterns that are spaced apart by the first distance between the first ones of plurality of active patterns and can include an extension that extends toward the substrate to below top surfaces of two of the plurality of active patterns that are spaced apart by the second distance between the two of the plurality of active patterns.
    Type: Application
    Filed: February 26, 2016
    Publication date: September 29, 2016
    Inventors: Changseop Yoon, SOON CHO
  • VERTICAL TYPE MEMORY DEVICE
    Publication number: 20160247818
    Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Inventors: Kwang-Soo Seol, Seong-Soon Cho
  • METHOD AND APPARATUS FOR ALLOCATING TRANSMISSION TIME FOR BI-DIRECTIONAL RELAY
    Publication number: 20160218795
    Abstract: A method and an apparatus for allocating a transmission time for a bi-directional relay are proposed. In a bi-directional relay system in which bi-directional communication is performed between a first node and a second node, basic parameters for transmission time allocation are acquired, where the basic parameters include a first transmission power of a signal transmitted from the first node and a second transmission power of a signal transmitted from the second node. A plurality of intersecting times at which sums of transmission rates for nodes become equal are calculated by using the basic parameters, and a transmission time is allocated based on the plurality of the intersecting times, the first transmission power, and the second transmission power.
    Type: Application
    Filed: January 25, 2016
    Publication date: July 28, 2016
    Inventor: Dae Soon Cho
  • Semiconductor device having a resistor and methods of forming the same
    Patent number: 9379115
    Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhyun Shin, Minchul Kim, Seong Soon Cho, Seungwook Chol
  • CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME
    Publication number: 20160162091
    Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.
    Type: Application
    Filed: February 10, 2016
    Publication date: June 9, 2016
    Inventors: JEONG-KYU HA, KWAN-JAi LEE, JAE-MIN JUNG, KYONG-SOON CHO, NA-RAE SHIN, KYOUNG-SUK YANG, PA-LAN LEE, SO-YOUNG LIM
  • Vertical type memory device
    Patent number: 9356044
    Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Seol, Seong-Soon Cho
  • METHOD AND APPARATUS FOR RECEIVING SIGNAL IN HIGH-SPEED MOBILE NETWORK
    Publication number: 20160128026
    Abstract: A method and an apparatus for receiving a signal in a high-speed mobile network are provided. In the case of receiving, by a moving terminal in a high-speed mobile network environment, signals transmitted from a plurality of base stations, a signal received through one antenna is decoded to generate a first symbol corresponding to a first signal transmitted from a first base station. The first symbol is subtracted from the received signal to acquire a modified received signal, and the modified received signal is decoded to generate a second symbol corresponding to a second signal transmitted from a second base station.
    Type: Application
    Filed: July 21, 2015
    Publication date: May 5, 2016
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dae Soon CHO, IL Gyu KIM, Seung Chan BANG
  • VERTICAL TYPE MEMORY DEVICE
    Publication number: 20160104721
    Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Inventors: Kwang-Soo SEOL, Seong-Soon CHO
  • Chip-on-film package and device assembly including the same
    Patent number: 9305990
    Abstract: Provided are a chip-on-film (COF) package and a device assembly including the same. The device assembly includes a COF package including a film substrate on which a plurality of film-through wires are formed. The device assembly includes a panel unit including a panel substrate on which a plurality of panel-through wires are formed. The panel unit is disposed on the COF package. One end of the panel unit is electrically connected to a first end of the COF package. The device assembly includes a control unit disposed below the panel unit. One end of the control unit is electrically connected to a second end of the COF package.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Min Jung, Kyong-Soon Cho, Jeong-Kyu Ha
  • Vertical type memory device
    Patent number: 9287167
    Abstract: A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Soo Seol, Seong Soon Cho, Byungjoo Go, Hongsoo Kim