Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: An operation method of a relay node may include: receiving, from a first communication node, first data composed of n bits; receiving, from a second communication node, second data composed of m bits; in response to determining that n is greater than m, generating first T-data of m bits excluding (n?m) bits from the n-bits of the first data and first R-data of (n?m) bits; generating third data by performing a network coding operation on the first T-data and the second data; transmitting the third data to the first communication node; and transmitting the third data and the first R-data to the second communication node.

Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.

Abstract: A display device includes a backlight unit including light source rows, each of the light source rows including light source blocks, a display panel configured to display an image by transmitting light emitted by the backlight unit, a panel driver configured to drive the display panel, and a backlight driver configured to drive the backlight unit. The backlight driver is configured to perform a vertical direction scan operation that sequentially select the light source rows and a horizontal direction sequential driving operation that sequentially drives the light source blocks included in a selected light source row of the light source rows.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Abstract: An operation method of a first terminal, performed in a communication system, may comprise receiving sidelink resource allocation information from a base station; receiving a first sidelink signal from a second terminal based on the sidelink resource allocation information; calculating a path loss experienced by the first sidelink signal based on the first sidelink signal; transmitting a second sidelink signal including information on the path loss experienced by the first sidelink signal to the second terminal; and receiving, from the second terminal, a third sidelink signal to which a sidelink transmit power determined based on the path loss is allocated.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.

Abstract: A display device includes a backlight unit including light source rows, each of the light source rows including light source blocks, a display panel configured to display an image by transmitting light emitted by the backlight unit, a panel driver configured to drive the display panel, and a backlight driver configured to drive the backlight unit. The backlight driver is configured to perform a vertical direction scan operation that sequentially select the light source rows and a horizontal direction sequential driving operation that sequentially drives the light source blocks included in a selected light source row of the light source rows.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

Abstract: An operation method of a first terminal, performed in a communication system, may comprise receiving sidelink resource allocation information from a base station; receiving a first sidelink signal from a second terminal based on the sidelink resource allocation information; calculating a path loss experienced by the first sidelink signal based on the first sidelink signal; transmitting a second sidelink signal including information on the path loss experienced by the first sidelink signal to the second terminal; and receiving, from the second terminal, a third sidelink signal to which a sidelink transmit power determined based on the path loss is allocated.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.