Patents by Inventor Srinivas D. Nemani

Srinivas D. Nemani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143323
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventors: Jong Mun KIM, Minrui YU, Chando PARK, Mang-Mang LING, Jaesoo AHN, Chentsau Chris YING, Srinivas D. NEMANI, Mahendra PAKALA, Ellie Y. YIEH
  • Patent number: 11003080
    Abstract: A method and apparatus disclosed herein apply to processing a substrate, and more specifically to a method and apparatus for improving photolithography processes. The apparatus includes a chamber body, a substrate support disposed within the chamber body, and an electrode assembly. The substrate support has a top plate disposed above the substrate support, a bottom plate disposed below the substrate support, and a plurality of electrodes connecting the top plate to the bottom plate. A voltage is applied to the plurality of electrodes to generate an electric field. Methods for exposing a photoresist layer on a substrate to an electric field are also disclosed herein.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Srinivas D. Nemani
  • Patent number: 10998200
    Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Mei-Yee Shek, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20210111222
    Abstract: Embodiments disclosed herein include CMOS image sensors and methods of forming such devices. In an embodiment, a method of forming a CMOS image sensor comprises pressurizing a chamber with a gas comprising hydrogen, and annealing a substrate in the pressurized chamber. In an embodiment the substrate comprises the CMOS image sensor. In an embodiment, the CMOS image sensor comprises a semiconductor body and a trench around a perimeter the semiconductor body, wherein the trench is filled with a high-k oxide that directly contacts the semiconductor body. In an embodiment, the method further comprises, depressurizing the chamber.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Inventors: Philip Hsin-hua Li, Toshihiko Miyashita, Ellie Yieh, Srinivas D. Nemani, Seshadri Ramaswami, Nikolaos Bekiaris
  • Publication number: 20210104434
    Abstract: Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.
    Type: Application
    Filed: October 6, 2019
    Publication date: April 8, 2021
    Inventors: He Ren, Hao Jiang, Mehul Naik, Srinivas D. Nemani, Ellie Yieh
  • Publication number: 20210104374
    Abstract: Apparatus for a multi-source ion beam etching (IBE) system are provided herein. In some embodiments, a multi-source IBE system includes a multi-source lid comprising a multi-source adaptor and a lower chamber adaptor, a plurality of IBE sources coupled to the multi-source adaptor, a rotary shield assembly coupled to a shield motor mechanism configured to rotate the rotary shield, wherein the shield motor mechanism is coupled to a top portion of the multi-source lid, and wherein the rotary shield includes a body that has one IBE source opening formed through the body, and at least one beam conduit that engages the one IBE source opening in the rotary shield on one end, and engages the bottom portion of the IBE sources on the opposite end of the beam conduit.
    Type: Application
    Filed: January 3, 2020
    Publication date: April 8, 2021
    Inventors: Qiwei Liang, Srinivas D. Nemani, Ellie Yieh, Douglas Buchberger, Chentsau Chris Ying
  • Publication number: 20210088896
    Abstract: Embodiments of the disclosure relate to lithography simulation and optical proximity correction. Field-guided post exposure bake processes have enabled improved lithography performance and various parameters of such processes are included in the optical proximity correction models generated in accordance with the embodiments described herein. An optical proximity correction model includes one or more parameters of anisotropic acid etching characteristics, ion generation and/or movement, electron movement, hole movement, and chemical reaction characteristics.
    Type: Application
    Filed: August 3, 2020
    Publication date: March 25, 2021
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Pinkesh Rohit SHAH, Srinivas D. NEMANI, Steven Hiloong WELCH, Christopher Siu Wing NGAI, Ellie Y. YIEH
  • Publication number: 20210090883
    Abstract: Methods and apparatus for depositing a dielectric material include: providing a first gas mixture into a processing chamber having a substrate disposed therein; forming a first remote plasma comprising first radicals in a remote plasma source and delivering the first radicals to an interior processing region in the processing chamber to form a layer of dielectric material in an opening in a material layer disposed on the substrate in a presence of the first gas mixture and the first radicals; terminating the first remote plasma and applying a first RF bias power to the processing chamber to form a first bias plasma; contacting the layer of dielectric material with the first bias plasma to form a first treated layer of dielectric material; and subsequently forming a second remote plasma comprising second radicals in the remote plasma source and delivering the second radicals to the interior processing region in the processing chamber in a presence of a second gas mixture while applying a second RF bias power t
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Inventors: Bhargav S. Citla, Jethro Tannos, Srinivas D. Nemani, Joshua Rubnitz
  • Patent number: 10957518
    Abstract: A plasma reactor includes a processing chamber having a lower processing portion having an axis of symmetry and an array of cavities extending upwardly from the lower processing portion. A gas distributor couples plural gas sources to a plurality of gas inlets of the cavities, and the gas distributor includes a plurality of valves with each valve selectively connecting a respective gas inlet to one of the plural gas sources. Power is applied by an array of conductors that includes a respective conductor for each respective cavity with each conductor adjacent and surrounding a cavity. A power distributor couples a power source and the array of conductors, and the power distributor includes a plurality of switches with a switch for each respective conductor.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Lawrence Wong, Steven Lane, Yang Yang, Srinivas D. Nemani, Praburam Gopalraja
  • Patent number: 10954594
    Abstract: The present disclosure generally relate to a semiconductor processing apparatus. In one embodiment, a processing chamber is disclosed herein. The processing chamber includes a chamber body and lid defining an interior volume, the lid configured to support a housing having a cap, a substrate support disposed in the interior volume, a vaporizer coupled to the cap and having an outlet open to the interior volume of the processing chamber, wherein the vaporizer is configured to deliver a precursor gas to a processing region defined between the vaporizer and the substrate support, and a heater disposed adjacent to the vaporizer, wherein the heater is configured to heat the vaporizer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Viachslav Babayan, Qiwei Liang, Tobin Kaufman-Osborn, Ludovic Godet, Srinivas D. Nemani
  • Patent number: 10947621
    Abstract: A method and apparatus for delivering gases to a semiconductor processing system are provided. In some embodiments, the apparatus includes a gas inlet line having an inlet valve; a gas outlet line having an outlet valve; a gas flow controller arranged to control the flow through the inlet valve; an orifice contained within at least one of the gas outlet line, the outlet valve, a chemical ampoule outlet valve, or outlet isolation valve; a chemical ampoule fluidly coupled to at least one of the gas inlet line and the gas outlet line; and a processing chamber. In some embodiments, the apparatus further includes a check valve, one or more orifices, and/or a heated divert line.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Adib Khan, Qiwei Liang, Srinivas D. Nemani, Tobin Kaufman-Osborn
  • Patent number: 10950429
    Abstract: Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhargav S. Citla, Mei-Yee Shek, Srinivas D. Nemani
  • Patent number: 10927449
    Abstract: Embodiments of the present disclosure provide a sputtering chamber with in-situ ion implantation capability. In one embodiment, the sputtering chamber comprises a target, an RF and a DC power supplies coupled to the target, a support body comprising a flat substrate receiving surface, a bias power source coupled to the support body, a pulse controller coupled to the bias power source, wherein the pulse controller applies a pulse control signal to the bias power source such that the bias power is delivered either in a regular pulsed mode having a pulse duration of about 100-200 microseconds and a pulse repetition frequency of about 1-200 Hz, or a high frequency pulsed mode having a pulse duration of about 100-300 microseconds and a pulse repetition frequency of about 200 Hz to about 20 KHz, and an exhaust assembly having a concentric pumping port formed through a bottom of the processing chamber.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jingjing Liu, Ludovic Godet, Srinivas D. Nemani, Yongmei Chen, Anantha K. Subramani
  • Publication number: 20210041785
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. A method of processing a substrate is provided. The method includes applying a photoresist layer that includes a photoacid generator to a multi-layer disposed on the substrate. The multi-layer includes an underlayer. Further, the method includes exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process. A thermal energy is provided to the photoresist layer and the multi-layer in a post-exposure baking process. The multi-layer is disposed beneath the photoresist layer. An electric field or a magnetic field is applied to photoresist layer and the multi-layer while performing the post-exposure baking process. An additive within the underlayer is driven in a vertical direction into the photoresist layer. The additive assist in distribution of a photoacid throughout the photoresist layer during the post-exposure baking process.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 11, 2021
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Pinkesh Rohit SHAH, Christopher Siu Wing NGAI, Srinivas D. NEMANI, Ellie Y. YIEH
  • Patent number: 10916426
    Abstract: Embodiments of the present disclosure relate to forming a two-dimensional crystalline dichalcogenide by positioning a substrate in an annealing apparatus. The substrate includes an amorphous film of a transition metal and a chalcogenide. The film is annealed at a temperature from 500° C. to 1200° C. In response to the annealing, a two-dimensional crystalline structure is formed from the film. The two-dimensional crystalline structure is according to a formula MX2, M includes one or more of molybdenum (Mo) or tungsten (W) and X includes one or more of sulfur (S), selenium (Se), or tellurium (Te).
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 9, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Keith Tatseun Wong, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 10916505
    Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yong Wu, Srinivas Gandikota, Abhijit Basu Mallick, Srinivas D. Nemani
  • Patent number: 10916433
    Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Maximillian Clemons, Mei-Yee Shek, Minrui Yu, Bencherki Mebarki, Mehul B. Naik, Chentsau Ying, Srinivas D. Nemani
  • Publication number: 20210035619
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: John O. DUKOVIC, Srinivas D. NEMANI, Ellie Y. YIEH, Praburam GOPALRAJA, Steven Hiloong WELCH, Bhargav S. CITLA
  • Publication number: 20210025058
    Abstract: Embodiments herein provide methods of plasma treating an amorphous silicon layer deposited using a flowable chemical vapor deposition (FCVD) process. In one embodiment, a method of processing a substrate includes plasma treating an amorphous silicon layer by flowing a substantially silicon-free hydrogen treatment gas into a processing volume of a processing chamber, the processing volume having the substrate disposed on a substrate support therein, forming a treatment plasma of the substantially silicon-free hydrogen treatment gas, and exposing the substrate having the amorphous silicon layer deposited on a surface thereof to the treatment plasma. Herein, the amorphous silicon layer is deposited using an FCVD process.
    Type: Application
    Filed: April 1, 2019
    Publication date: January 28, 2021
    Inventors: Shishi JIANG, Pramit MANNA, Abhijit Basu MALLICK, Suresh Chand SETH, Srinivas D. NEMANI
  • Patent number: 10892161
    Abstract: Methods for depositing desired materials formed on certain locations of a substrate with desired materials using a selective deposition process for semiconductor applications are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes supplying a first gas comprising a hydroxy terminated hydrocarbon containing material to a surface of a substrate, selectively forming a passivation layer on a first material of the substrate, selectively forming self assembled monolayers on a second material of the substrate, and selectively forming a material layer on the passivation layer.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Biao Liu, Cheng Pan, Erica Chen, Srinivas D. Nemani, Chang Ke, Lei Zhou