Abstract: Generally, examples described herein relate to methods and processing systems for performing multiple processes in a same processing chamber on a flowable gap-fill film deposited on a substrate. In an example, a semiconductor processing system includes a processing chamber and a system controller. The system controller includes a processor and memory. The memory stores instructions, that when executed by the processor cause the system controller to: control a first process within the processing chamber performed on a substrate having thereon a film deposited by a flowable process, and control a second process within the process chamber performed on the substrate having thereon the film. The first process includes stabilizing bonds in the film to form a stabilized film. The second process includes densifying the stabilized film.

Abstract: Disclosed herein is an electrostatic chuck (ESC) carrier. The ESC carrier may comprise a carrier substrate having a first surface and a second surface opposite the first surface. A first through substrate opening and a second through substrate opening may pass through the carrier substrate from the first surface to the second surface. A first conductor is in the first through substrate opening, and a second conductor is in the second through substrate opening. The ESC carrier may further comprise a first electrode over the first surface of the carrier substrate and electrically coupled to the first conductor, and a second electrode over the first surface of the carrier substrate and electrically coupled to the second conductor. An oxide layer may be formed over the first electrode and the second electrode.

Abstract: A method of etching a layer stack. The method may include providing a substrate in a process chamber, the substrate comprising an array of patterned features, arranged within a layer stack, the layer stack including at least one metal layer, and directing an ion beam to the substrate from an ion source, wherein the ion beam causes a physical sputtering of the at least one metal layer. The method may include directing a neutral reactive gas directly to the substrate, separately from the ion source, wherein the neutral reactive gas reacts with metallic species generated by the physical sputtering of the at least one metal layer.

Abstract: The present disclosure generally relates to a pin-less substrate transfer apparatus and method for a processing chamber. The processing chamber includes a pedestal. The pedestal includes a pedestal plate. The pedestal plate has a radius, a top surface, and a bottom surface. The pedestal plate further includes a plurality of cut outs on a perimeter of the pedestal plate. Flat edges are disposed on opposite sides of the pedestal plate. Recesses are disposed in the bottom surface below each of the flat edges.

Abstract: Implementations described herein relate to apparatus and methods for self-assembled monolayer (SAM) deposition. Apparatus described herein includes processing chambers having various vapor phase delivery apparatus fluidly coupled thereto. SAM precursors may be delivered to process volumes of the chambers via various apparatus which is heated to maintain the precursors in vapor phase. In one implementation, a first ampoule or vaporizer configured to deliver a SAM precursor may be fluidly coupled to the process volume of a process chamber. A second ampoule or vaporizer configured to deliver a material different from the SAM precursor may also be fluidly coupled to the process volume of the process chamber.

Abstract: A method and apparatus for depositing a carbon compound on a substrate includes using an inductively coupled plasma (ICP) chamber with a chamber body, a lid, an interior volume, a pumping apparatus, and a gas delivery system and a pedestal for supporting a substrate disposed within the interior volume of the ICP chamber, the pedestal has an upper portion formed from aluminum nitride with an upper surface that is configured to support and heat a substrate with embedded heating elements and a lower portion with a tube-like structure formed from aluminum nitride that is configured to support the upper portion and house electrodes for supplying power to the embedded heating elements of the upper portion, and the pedestal is configured to heat the substrate during deposition of a carbon compound film.

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

Abstract: Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

Abstract: A method and apparatus disclosed herein apply to processing a substrate, and more specifically to a method and apparatus for improving photolithography processes. The apparatus includes a chamber body, a substrate support disposed within the chamber body, and an electrode assembly. The substrate support has a top plate disposed above the substrate support, a bottom plate disposed below the substrate support, and a plurality of electrodes connecting the top plate to the bottom plate. A voltage is applied to the plurality of electrodes to generate an electric field. Methods for exposing a photoresist layer on a substrate to an electric field are also disclosed herein.

Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

Abstract: Embodiments disclosed herein include CMOS image sensors and methods of forming such devices. In an embodiment, a method of forming a CMOS image sensor comprises pressurizing a chamber with a gas comprising hydrogen, and annealing a substrate in the pressurized chamber. In an embodiment the substrate comprises the CMOS image sensor. In an embodiment, the CMOS image sensor comprises a semiconductor body and a trench around a perimeter the semiconductor body, wherein the trench is filled with a high-k oxide that directly contacts the semiconductor body. In an embodiment, the method further comprises, depressurizing the chamber.

Abstract: Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

Abstract: Apparatus for a multi-source ion beam etching (IBE) system are provided herein. In some embodiments, a multi-source IBE system includes a multi-source lid comprising a multi-source adaptor and a lower chamber adaptor, a plurality of IBE sources coupled to the multi-source adaptor, a rotary shield assembly coupled to a shield motor mechanism configured to rotate the rotary shield, wherein the shield motor mechanism is coupled to a top portion of the multi-source lid, and wherein the rotary shield includes a body that has one IBE source opening formed through the body, and at least one beam conduit that engages the one IBE source opening in the rotary shield on one end, and engages the bottom portion of the IBE sources on the opposite end of the beam conduit.

Abstract: Embodiments of the disclosure relate to lithography simulation and optical proximity correction. Field-guided post exposure bake processes have enabled improved lithography performance and various parameters of such processes are included in the optical proximity correction models generated in accordance with the embodiments described herein. An optical proximity correction model includes one or more parameters of anisotropic acid etching characteristics, ion generation and/or movement, electron movement, hole movement, and chemical reaction characteristics.

Abstract: Methods and apparatus for depositing a dielectric material include: providing a first gas mixture into a processing chamber having a substrate disposed therein; forming a first remote plasma comprising first radicals in a remote plasma source and delivering the first radicals to an interior processing region in the processing chamber to form a layer of dielectric material in an opening in a material layer disposed on the substrate in a presence of the first gas mixture and the first radicals; terminating the first remote plasma and applying a first RF bias power to the processing chamber to form a first bias plasma; contacting the layer of dielectric material with the first bias plasma to form a first treated layer of dielectric material; and subsequently forming a second remote plasma comprising second radicals in the remote plasma source and delivering the second radicals to the interior processing region in the processing chamber in a presence of a second gas mixture while applying a second RF bias power t

Abstract: A plasma reactor includes a processing chamber having a lower processing portion having an axis of symmetry and an array of cavities extending upwardly from the lower processing portion. A gas distributor couples plural gas sources to a plurality of gas inlets of the cavities, and the gas distributor includes a plurality of valves with each valve selectively connecting a respective gas inlet to one of the plural gas sources. Power is applied by an array of conductors that includes a respective conductor for each respective cavity with each conductor adjacent and surrounding a cavity. A power distributor couples a power source and the array of conductors, and the power distributor includes a plurality of switches with a switch for each respective conductor.

Abstract: The present disclosure generally relate to a semiconductor processing apparatus. In one embodiment, a processing chamber is disclosed herein. The processing chamber includes a chamber body and lid defining an interior volume, the lid configured to support a housing having a cap, a substrate support disposed in the interior volume, a vaporizer coupled to the cap and having an outlet open to the interior volume of the processing chamber, wherein the vaporizer is configured to deliver a precursor gas to a processing region defined between the vaporizer and the substrate support, and a heater disposed adjacent to the vaporizer, wherein the heater is configured to heat the vaporizer.