Patents by Inventor Srinivas V. Pietambaram

Srinivas V. Pietambaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098503
    Abstract: Various embodiments include, for example, a magnetic-dielectric film-based inductor that can be embedded in an electronic package for use as an integrated voltage-regulator, multiple conductive regions to provide electrical interconnects to the magnetic-dielectric-based inductor from other devices, multiple conductive pillars that are electrically coupled to and formed over at least some of the conductive regions, and a magnetic-dielectric layer formed over at least some of conductive regions and conductive pillars. The magnetic-dielectric layer is formed by a multi-layer formation technique having multiple dielectric-material layers and multiple magnetic-material layers. Each of the magnetic-material layers is interspersed with at least one of the dielectric-material layers. Other devices, apparatuses, and methods are described.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Srinivas V. Pietambaram, Kristof Darmawikarta, Rahul N. Manepalli
  • Publication number: 20200091053
    Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Srinivas V. Pietambaram, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Krishna Bharath, Michael James Hill
  • Publication number: 20200075473
    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.
    Type: Application
    Filed: May 23, 2017
    Publication date: March 5, 2020
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, David Unruh, Frank Truong, Kyu Oh Lee, Junnan Zhao, Sri Chaitra Jyotsna Chavali
  • Publication number: 20190393145
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 26, 2019
    Inventors: Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
  • Publication number: 20190393178
    Abstract: An electroless nickel, electroless palladium, electroless tin stack and. associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Inventors: David Unruh, Srinivas V. Pietambaram
  • Publication number: 20190393172
    Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.
    Type: Application
    Filed: March 30, 2017
    Publication date: December 26, 2019
    Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Aleksandar ALEKSOV, Telesphor KAMGAING
  • Publication number: 20190371621
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20190363063
    Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.
    Type: Application
    Filed: December 30, 2016
    Publication date: November 28, 2019
    Applicant: Intel Corporation
    Inventors: Robert Alan MAY, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
  • Patent number: 10477688
    Abstract: A stretchable electronic assembly comprising a stretchable body, a plurality of electronic components encapsulated in the stretchable body, at least one meandering conductor connected to at least one electronic component of the plurality of electronic components, at least one hollow pocket formed in the stretchable body, the at least one meandering conductor encapsulated in the stretchable body and the at least one meandering conductor located within the at least one hollow pocket formed in the stretchable body.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Srinivas V. Pietambaram, Rahul N. Manepalli
  • Publication number: 20190333861
    Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 31, 2019
    Inventors: Srinivas V. Pietambaram, Rahul N. Manapalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
  • Patent number: 10438914
    Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: David Unruh, Srinivas V. Pietambaram
  • Publication number: 20190287915
    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include forming a first conductive trace adjacent a second conductive trace on a dielectric material of a high density package substrate. A barrier layer is formed on at least one of the first conductive trace or the second conductive trace, wherein the barrier layer comprises a corrosion resistant material, and forming a conductive via on a portion of the barrier layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: David Unruh, Srinivas V. Pietambaram
  • Publication number: 20190279935
    Abstract: Semiconductor packages including package substrates having non-homogeneous dielectric layers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package substrate includes a dielectric layer having a resin-rich region, e.g., a resin-rich sublayer, and a filler-rich region, e.g., a filler-rich sublayer. The sublayers may contain respective mixtures of an organic resin material and an inorganic filler material. The filler-rich sublayer may have a higher density of the inorganic filler material than the resin-rich sublayer. A density of the inorganic filler material may be lesser near a top surface of 0 the dielectric layer in which an electrical interconnect is embedded. The electrical interconnect may have a greater adhesion affinity to the organic resin material than the inorganic filler material, and thus, the electrical interconnect may readily attach to the functionally-graded dielectric layer.
    Type: Application
    Filed: December 29, 2016
    Publication date: September 12, 2019
    Inventors: David Allen UNRUH, JR., Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI
  • Publication number: 20190281717
    Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.
    Type: Application
    Filed: September 28, 2016
    Publication date: September 12, 2019
    Inventors: Aleksandar Aleksov, Son V. Nguyen, Rajat Goyal, David B. Lampner, Dilan Seneviratne, Albert S. Lopez, Joshua D. Heppner, Srinivas V. Pietambaram, Shawna M. Liff, Nadine L. Dabby
  • Publication number: 20190259631
    Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: August 22, 2019
    Inventors: Robert Alan MAY, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati, Sandeep Gaan, Srinivas V. Pietambaram
  • Publication number: 20190206791
    Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.
    Type: Application
    Filed: July 1, 2016
    Publication date: July 4, 2019
    Inventors: Srinivas V. Pietambaram, Rahul N Manepalli
  • Publication number: 20190206786
    Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Sandeep GAAN, Srinivas V. PIETAMBARAM, Sameer R. PAITAL
  • Publication number: 20190189563
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: September 29, 2016
    Publication date: June 20, 2019
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Publication number: 20190123266
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Srinivas V. PIETAMBARAM, Bengt J. AKERMAN, Renu WHIG, Jason A. JANESKY, Nicholas D. RIZZO, Jon M. SLAUGHTER
  • Patent number: 10199571
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: February 5, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter