Patents by Inventor Srinivas V. Pietambaram

Srinivas V. Pietambaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150280110
    Abstract: An MRAM bit includes a free magnetic region, a fixed magnetic region comprising an anti-ferromagnetic material, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, (ii) a second layer of one or more ferromagnetic materials wherein the one or more ferromagnetic materials includes cobalt, (iii) a third layer of one or more ferromagnetic materials, and an anti-ferromagnetic coupling layer, wherein: (a) the anti-ferromagnetic coupling layer is disposed between the first and third layers, and (b) the second layer is disposed between the first layer and the anti-ferromagnetic coupling layer.
    Type: Application
    Filed: June 2, 2015
    Publication date: October 1, 2015
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 9093637
    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 28, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Publication number: 20150021606
    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
    Type: Application
    Filed: June 12, 2014
    Publication date: January 22, 2015
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason Janesky, Nicholas D. Rizzo, Jon Slaughter
  • Patent number: 8754460
    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 17, 2014
    Assignee: EverSpin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Publication number: 20140021471
    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
    Type: Application
    Filed: June 24, 2013
    Publication date: January 23, 2014
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu W. Dave, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 8497538
    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: July 30, 2013
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu W. Dave, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 7684161
    Abstract: A synthetic antiferromagnet (SAF) structure includes a first ferromagnetic layer, a first insertion layer, a coupling layer, a second insertion layer, and a second ferromagnetic layer. The insertion layers comprise materials selected such that SAF exhibits reduced temperature dependence of antiferromagnetic coupling strength. The insertion layers may include CoFe or CoFeX alloys. The thickness of the insertion layers is selected such that they do not increase the uniaxial anisotropy or deteriorate any other properties.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 23, 2010
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Renu W. Dave, Jon M. Slaughter, JiJun Sun
  • Patent number: 7683445
    Abstract: Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD) material (106, 108, 110, 158, 160, 162, 458, 460, 462) disposed adjacent the magnetoelectronic device. The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprises multiple composite layers (408) of magnetic nano-particles (406) embedded in a dielectric matrix (409). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device (102, 152, 452) and depositing the programming line (104, 154, 156, 454, 456).
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 23, 2010
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 7635902
    Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: December 22, 2009
    Assignee: Everspin Technologies, Inc.
    Inventors: Nicholas D. Rizzo, Renu Dave, Jon M. Slaughter, Srinivas V. Pietambaram
  • Publication number: 20090121266
    Abstract: Exchange-coupled magnetic multilayer structures for use with toggle MRAM devices and the like include a tunnel barrier layer (108) and a synthetic antiferromagnet (SAF) structure (300) formed on the tunnel barrier layer (108), wherein the SAF (300) includes a plurality (e.g., four or more) of ferromagnetic layers (302, 306, 310, 314) antiferromagnetically or ferromagnetically coupled by a plurality of respective coupling layers (304, 308, 312). The microcrystalline texture of one or more of the ferromagnetic layers is reduced to substantially zero as measured from X-Ray Diffraction by exposure of various layers to oxygen, by forming a detexturing layer, by adding oxygen during the ferromagnetic or coupling layer fabrication, and/or by using amorphous materials.
    Type: Application
    Filed: November 13, 2007
    Publication date: May 14, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Srinivas V. Pietambaram, Jason A. Janesky, Jon M. Slaughter, Jijun Sun
  • Patent number: 7445943
    Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: November 4, 2008
    Assignee: Everspin Technologies, Inc.
    Inventors: Kenneth H. Smith, Brian R. Butcher, Gregory W. Grynkewich, Srinivas V. Pietambaram, Nicholas D. Rizzo
  • Publication number: 20080096290
    Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventors: Kenneth H. Smith, Brian R. Butcher, Gregory W. Grynkewich, Srinivas V. Pietambaram, Nicholas D. Rizzo
  • Publication number: 20070278547
    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 6, 2007
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu W. Dave, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 7285835
    Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: October 23, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nicholas D. Rizzo, Renu Dave, Jon M. Slaughter, Srinivas V. Pietambaram
  • Patent number: 7226796
    Abstract: A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: June 5, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Srinivas V. Pietambaram, Renu W. Dave, Jon M. Slaughter, Jijun Sun
  • Patent number: 7067331
    Abstract: An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: June 27, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jon M. Slaughter, Renu W. Dave, Srinivas V. Pietambaram
  • Patent number: 6946697
    Abstract: A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: September 20, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Srinivas V. Pietambaram, Renu W. Dave, Jon M. Slaughter, Jijun Sun
  • Patent number: 6831312
    Abstract: An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: December 14, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jon M. Slaughter, Renu W. Dave, Srinivas V. Pietambaram
  • Publication number: 20040041183
    Abstract: An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 4, 2004
    Inventors: Jon M. Slaughter, Renu W. Dave, Srinivas V. Pietambaram
  • Patent number: 6541280
    Abstract: A dielectric layer comprises lanthanum, aluminum and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with respect to the lanthanum or aluminum. In another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: April 1, 2003
    Assignee: Motorola, Inc.
    Inventors: Vidya S. Kaushik, Bich-yen Nguyen, Srinivas V. Pietambaram, James Kenyon Schaeffer, III