Patents by Inventor Srivatsan Parthasarathy

Srivatsan Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9954356
    Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: April 24, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Rodrigo Carrillo-Ramirez
  • Patent number: 9952852
    Abstract: Deployment and servicing tasks associated with multi-tier, distributed applications, application environments and data centers are automated so that a person does not have to manually perform these tasks. All of the information describing and defining the distributed service is modeled and stored in a re-useable service template that can be used to drive an automated system to programmatically deploy and manage the service over time. Deployment and servicing of a distributed application can be automated using re-useable models that capture hardware and workload definitions. The re-useable models in the form of service templates enable delta-based servicing of the application. The service can be deployed to one or more physical machines, one or more virtual machines or to a combination thereof. A default deployment plan can be customized with instance-specific customizations of service parameters.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 24, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William L. Scheidel, Robert M. Fries, Srivatsan Parthasarathy, Alan C. Shi, James P. Finnigan
  • Publication number: 20180083439
    Abstract: Micro-electromechanical switch (MEMS) devices can be fabricated using integrated circuit fabrication techniques and materials. Such switch devices can provide cycle life and insertion loss performance suiting for use in a broad range of applications including, for example, automated test equipment (ATE), switching for measurement instrumentation (such as a spectrum analyzer, network analyzer, or communication test system), and uses in communication systems, such as for signal processing. MEMS devices can be vulnerable to electrical over-stress, such as associated with electrostatic discharge (ESD) transient events. A solid-state clamp circuit can be incorporated in a MEMS device package to protect one or more MEMS devices from damaging overvoltage conditions. The clamp circuit can include single or multiple blocking junction structures having complementary current-voltage relationships, such as to help linearize a capacitance-to-voltage relationship presented by the clamp circuit.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Padraig Liam Fitzgerald, Srivatsan Parthasarathy, Javier A. Salcedo
  • Publication number: 20180026440
    Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 25, 2018
    Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Publication number: 20170366002
    Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 21, 2017
    Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 9831666
    Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 28, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Rodrigo Carrillo-Ramirez
  • Patent number: 9807129
    Abstract: A logical communication path is provided between a target virtual machine (VM) and a host or application communicating with the VM. The target VM runs on a hypervisor host that has a hypervisor and a proxy agent. The hypervisor manages execution of the VM. A mapping is maintained indicating which VMs execute on which hosts. When the host or application is to send a message or packet to the target VM, the mapping is consulted and the hypervisor host hosting the target VM is identified. The message or packet, which may identify the target VM, is transmitted to the hypervisor host. A proxy agent at the hypervisor host selects a communication channel between the hypervisor and the target VM. The hypervisor then passes the message or packet through the selected channel to the target VM.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 31, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Robert Fries, Srivatsan Parthasarathy, Ashvinkumar Sanghvi, Aravind Ramarathinam, Michael Grier
  • Publication number: 20170256534
    Abstract: Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant actively-controlled protection circuit includes a transient overstress detection circuit, a clamp circuit electrically connected between a first node and a second node, a bias circuit that biases the clamp circuit, and a false condition shutdown circuit. The transient overstress detection circuit generates a detection signal indicating whether or not a transient overstress event is detected between the first and second nodes. Additionally, the false condition shutdown circuit generates a false condition shutdown signal based on low pass filtering a voltage difference between the first and second nodes, thereby determining independently whether or not power is present. The bias circuit controls operation of the clamp circuit in an on state or an off state based on the detection signal and the false condition shutdown signal.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 7, 2017
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Publication number: 20170243862
    Abstract: Apparatus and methods for compound semiconductor protection clamps are provided herein. In certain configurations, a compound semiconductor protection clamp includes a resistor-capacitor (RC) trigger network and a metal-semiconductor field effect transistor (MESFET) clamp. The RC trigger network detects when an ESD/EOS event is present between a first node and a second node, and activates the MESFET clamp in response to detecting the ESD/EOS event. When the MESFET clamp is activated, the MESFET clamp provides a low impedance path between the first and second nodes, thereby providing ESD/EOS protection. When deactivated, the MESFET clamp provides high impedance between the first and second nodes, and thus operates with low leakage current and small static power dissipation.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 24, 2017
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Publication number: 20170169080
    Abstract: Analyzing log data. The method includes obtaining a first bucket of a log data. The first bucket of log data includes a plurality of log lines. The method further includes analyzing the first bucket of log data to identify different sets of similar log lines. The method further includes providing to a user in a user interface one or more summaries of the different sets of similar lines. The summary comprises at least one user selectable indicator representing differences in log lines in a set of similar log lines that when selected by a user in the user interface reveals specific differences in the log lines in the set of similar log lines.
    Type: Application
    Filed: April 15, 2016
    Publication date: June 15, 2017
    Inventors: Srivatsan Parthasarathy, Rohit Bhardwaj, Chirag Gupta, Vipul Malhotra, Evan Herschel Brodie Hissey
  • Publication number: 20170155685
    Abstract: A method includes acts for establishing a subscription for an entity. The method includes receiving, at a cloud service provider, a request from an entity to establish a subscription. The request includes credentials for the entity that are not proper credentials for an organization associated with the entity that the entity should use to access services for the organization. The method further includes performing a corrective action based on detecting one or more factors to determine that the entity is associated with the organization. The method further includes providing services based on the corrective action.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 1, 2017
    Inventors: Ranganathan Srikanth, David James Armour, Ashvinkumar J. Sanghvi, Jeremy Winter, John David Ballard, Dwayne Richard Need, Srivatsan Parthasarathy
  • Patent number: 9634482
    Abstract: Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 25, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Sandro Herrera
  • Patent number: 9596267
    Abstract: A method includes acts for establishing a subscription for an entity. The method includes receiving, at a cloud service provider, a request from an entity to establish a subscription. The request includes credentials for the entity that are not proper credentials for an organization associated with the entity that the entity should use to access services for the organization. The method further includes performing a corrective action based on detecting one or more factors to determine that the entity is associated with the organization. The method further includes providing services based on the corrective action.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 14, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ranganathan Srikanth, David James Armour, Ashvinkumar J. Sanghvi, Jeremy Winter, John David Ballard, Dwayne Richard Need, Srivatsan Parthasarathy
  • Publication number: 20160336744
    Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 17, 2016
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Rodrigo Carrillo-Ramirez
  • Publication number: 20160336740
    Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 17, 2016
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Rodrigo Carrillo-Ramirez
  • Patent number: 9438033
    Abstract: Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 6, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Rodrigo Carrillo-Ramirez
  • Publication number: 20160248818
    Abstract: A logical communication path is provided between a target virtual machine (VM) and a host or application communicating with the VM. The target VM runs on a hypervisor host that has a hypervisor and a proxy agent. The hypervisor manages execution of the VM. A mapping is maintained indicating which VMs execute on which hosts. When the host or application is to send a message or packet to the target VM, the mapping is consulted and the hypervisor host hosting the target VM is identified. The message or packet, which may identify the target VM, is transmitted to the hypervisor host. A proxy agent at the hypervisor host selects a communication channel between the hypervisor and the target VM. The hypervisor then passes the message or packet through the selected channel to the target VM.
    Type: Application
    Filed: October 30, 2015
    Publication date: August 25, 2016
    Inventors: Robert Fries, Srivatsan Parthasarathy, Ashvinkumar Sanghvi, Aravind Ramarathinam, Michael Grier
  • Patent number: 9362265
    Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: June 7, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 9342326
    Abstract: A system in which a virtual machine manager determines tasks that are to be performed on virtual machines executing on a host computing system. The host computing system further executes an intermediary virtual machine task management module that receives virtual machine tasks from the virtual machine manager. Upon request from the virtual machines, the intermediary module identifies the tasks that are to be performed on the requesting virtual machine to the requesting virtual machine. The virtual machines may perhaps also initiate the performance of such identified tasks. Since the virtual machine itself is initiating contact with the intermediary module, and is not interacting directly with the virtual machine manager, the virtual machine manager need not be in the same sphere of trust as the virtual machine.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 17, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aravind Ramarathinam, Srivatsan Parthasarathy
  • Publication number: 20160117160
    Abstract: The present invention extends to methods, systems, and computer program products for preparing installations and updates for software systems. Aspects of the invention include creating software update packages that are selectable to automatically install essentially any number of code changes for any number of software components to update a software system (e.g., a cloud appliance). In one aspect, a software update package includes: references to code changes for a plurality of software components and references to installation artifacts for installing the code changes, and also indicates interdependencies between the plurality of software components. In another aspect, a software update package includes references to validation code for validating that a software update package transitioned a software system to a goal state.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Srivatsan Parthasarathy, Jeffrey Scott Zabel, Mohanish Rajesh Penta, Kiran Isaac Abraham, Spencer James Clark, Haojie Hang, Mokhtar M. Khorshid, Filippo Seracini, Justin R. Incarnato