Patents by Inventor Srivatsan Parthasarathy

Srivatsan Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160117161
    Abstract: The present invention extends to methods, systems, and computer program products for installing and updating software systems. Aspects of the invention include selecting software update packages that automatically installs essentially any number of code changes for any number of software components to update a software system (e.g., a cloud appliance). In one aspect, a software system is updated by implementing a software update package that includes: references to code changes for a plurality of software components and references to installation artifacts for installing the code changes, and also indicates interdependencies between the plurality of software components. In another aspect, validation code is used to validate that a software update package transitioned a software system to a goal state. In a further aspect, a multi-pass installation process is orchestrated to perform portions of a software update package in a plurality of different passes.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Srivatsan Parthasarathy, Jeffrey Scott Zabel, Mohanish Rajesh Penta, Kiran Isaac Abraham, Spencer James Clark, Haojie Hang, Mokhtar M. Khorshid, Filippo Seracini, Justin R. Incarnato
  • Patent number: 9317279
    Abstract: Techniques are described to allow substation of blocks into a virtual machine image of an executing virtual machine. A patch may be applied to a first virtual machine image. One or more blocks modified by the patch are identified and copied to a host having a virtual machine executing from a virtual machine image that is based on the first virtual machine image (prior to the patch). While the virtual machine is executing, the substitution blocks are applied (supersede) corresponding original blocks in the virtual machine image. A guest operating system in the virtual machine may either begin using an executable file in a substitution block. In addition, the guest operating system may be forced to flush from memory and cache executable code replaced by the substitution block.
    Type: Grant
    Filed: June 7, 2014
    Date of Patent: April 19, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Robert Fries, Srivatsan Parthasarathy
  • Patent number: 9293912
    Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 22, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Publication number: 20160065616
    Abstract: A method includes acts for establishing a subscription for an entity. The method includes receiving, at a cloud service provider, a request from an entity to establish a subscription. The request includes credentials for the entity that are not proper credentials for an organization associated with the entity that the entity should use to access services for the organization. The method further includes performing a corrective action based on detecting one or more factors to determine that the entity is associated with the organization. The method further includes providing services based on the corrective action.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Ranganathan Srikanth, David James Armour, Ashvinkumar J. Sanghvi, Jeremy Winter, John David Ballard, Dwayne Richard Need, Srivatsan Parthasarathy
  • Publication number: 20160026457
    Abstract: Deployment and servicing tasks associated with multi-tier, distributed applications, application environments and data centers are automated so that a person does not have to manually perform these tasks. All of the information describing and defining the distributed service is modeled and stored in a re-useable service template that can be used to drive an automated system to programmatically deploy and manage the service over time. Deployment and servicing of a distributed application can be automated using re-useable models that capture hardware and workload definitions. The re-useable models in the form of service templates enable delta-based servicing of the application. The service can be deployed to one or more physical machines, one or more virtual machines or to a combination thereof. A default deployment plan can be customized with instance-specific customizations of service parameters.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventors: WILLIAM L. SCHEIDEL, ROBERT M. FRIES, SRIVATSAN PARTHASARATHY, ALAN C. SHI, JAMES P. FINNIGAN
  • Publication number: 20160020603
    Abstract: Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Sandro Herrera
  • Patent number: 9207962
    Abstract: Techniques for analyzing virtual machine images are described. In one embodiment, a subset of settings is extracted from one or more virtual machine images, the virtual machine images store therein values of the settings. The settings are used by software executing in virtual machines of the virtual machine images, respectively. A target one of the virtual machine images is selected and target values of the settings are obtained from the target virtual machine image. Sample values of the settings are obtained from a plurality of virtual machine images. The subset formed by identifying similarities and differences of the values between the virtual machine images.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 8, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Robert Fries, Galen Hunt, Srivatsan Parthasarathy
  • Patent number: 9191454
    Abstract: A logical communication path is provided between a target virtual machine (VM) and a host or application communicating with the VM. The target VM runs on a hypervisor host that has a hypervisor and a proxy agent. The hypervisor manages execution of the VM. A mapping is maintained indicating which VMs execute on which hosts. When the host or application is to send a message or packet to the target VM, the mapping is consulted and the hypervisor host hosting the target VM is identified. The message or packet, which may identify the target VM, is transmitted to the hypervisor host. A proxy agent at the hypervisor host selects a communication channel between the hypervisor and the target VM. The hypervisor then passes the message or packet through the selected channel to the target VM.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: November 17, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Robert Fries, Srivatsan Parthasarathy, Ashvinkumar Sanghvi, Aravind Ramarathinam, Michael Grier
  • Patent number: 9184098
    Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: November 10, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy, Shuyun Zhang
  • Patent number: 9152402
    Abstract: Deployment and servicing tasks associated with multi-tier, distributed applications, application environments and data centers are automated so that a person does not have to manually perform these tasks. All of the information describing and defining the distributed service is modeled and stored in a re-useable service template that can be used to drive an automated system to programmatically deploy and manage the service over time. Deployment and servicing of a distributed application can be automated using re-useable models that capture hardware and workload definitions. The re-useable models in the form of service templates enable delta-based servicing of the application. The service can be deployed to one or more physical machines, one or more virtual machines or to a combination thereof. A default deployment plan can be customized with instance-specific customizations of service parameters.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 6, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING LLC.
    Inventors: William L. Scheidel, Robert M. Fries, Srivatsan Parthasarathy, Alan C. Shi, James P. Finnigan
  • Patent number: 9123540
    Abstract: Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: September 1, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 9076807
    Abstract: In one embodiment, an apparatus includes a package that encompasses at least a first integrated circuit die and a second integrated circuit die. The first integrated circuit die is attached to the package and includes one or more electrical overstress/electrostatic discharge (EOS/ESD) protection circuits. The second integrated circuit die is attached to the package and electrically coupled to the first integrated circuit die such that at least one component of the second integrated circuit die is protected from EOS/ESD by the first integrated circuit die.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 7, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Charly El-Khoury, Francisco Santos, Nathan R. Carter
  • Publication number: 20150138678
    Abstract: Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Rodrigo Carrillo-Ramirez
  • Publication number: 20150115317
    Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.
    Type: Application
    Filed: January 9, 2015
    Publication date: April 30, 2015
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 9006781
    Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 14, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Publication number: 20150076557
    Abstract: Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.
    Type: Application
    Filed: October 31, 2013
    Publication date: March 19, 2015
    Applicant: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Publication number: 20150070806
    Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Patent number: 8958187
    Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit can generate a first activation signal in response to a transient electrical stress event across a first node and a second node. A blocking circuit is configured to bias the base of a first driver bipolar transistor to slow down discharge of accumulated base charge of a first driver bipolar transistor, which permits the first driver bipolar transistor to remain activated for a longer period of time than had the base of the first driver bipolar transistor been biased to the same voltage as the emitter of the first bipolar transistor. Shut-off circuitry can be included in some embodiments to prevent a discharge circuit from activating during normal operating conditions.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo
  • Patent number: 8946822
    Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: February 3, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Srivatsan Parthasarathy
  • Patent number: 8878344
    Abstract: Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: November 4, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Shuyun Zhang