Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: A molding comprising a mixed oxide, wherein the mixed oxide comprises oxygen, lanthanum, aluminum, and cobalt, wherein in the mixed oxide, the weight ratio of cobalt relative to aluminum, calculated as elements, is at least 0.17:1. A preparation method by a dry route. Use of the molding as a catalyst for the reforming of hydrocarbons into a synthesis gas.

Abstract: A DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and a compensation circuit. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representative of a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit is coupled to the error amplifier. The compensation circuit includes a resistor, a capacitor, and a switch control circuit. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switch control circuit is configured to modulate connection of the resistor to the capacitor based on a switching frequency of the DC-DC converter.

Abstract: Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.

Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.

Abstract: A furniture component and method of manufacturing the same, the furniture component having a wall with at least two opposite side faces and a multitude of front faces. On the wall between the side faces, a takeup space is configured which accommodates a set of fittings for guiding a movable furniture element. The set of fittings includes a multitude of fitting components and can be transferred to at least two positions. The takeup space includes aperture sections in at least two front faces of the wall, where the takeup space is outwardly open. The set of fittings is configured and set up such that during transfer of the set of fittings from the first position to the second position, the set of fittings moves at least in the aperture sections in the at least two front faces.

Abstract: Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.

Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.

Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.

Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.

Abstract: To facilitate current sensing for valley current-controlled power converters, an example apparatus includes a comparator having a first terminal, a second terminal, and an output. A first transistor has a first drain coupled to the first terminal of the comparator. A second transistor has a second drain coupled to the first terminal of the comparator. A third transistor has a third drain coupled to the second terminal of the comparator.

Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cir

Abstract: A gate-charge harvester includes a harvest capacitor that has a first plate and a second plate. The second plate is coupled to a lower rail and the first plate is coupled to send a voltage towards a regulator. The gate-charge harvester also includes a low-side harvest transistor having a first terminal coupled to a gate of a low-side power transistor and a second terminal coupled to the first plate.

Abstract: Methods, systems, and apparatus to facilitate current sensing for valley current-controlled power converters are disclosed. An example apparatus includes a comparator including a first terminal, a second terminal, and an output. The apparatus further includes a first transistor including a first drain coupled to the first terminal of the comparator. The apparatus further includes a second transistor including a second drain coupled to the first terminal of the comparator. The apparatus further includes a third transistor including a third drain coupled to the second terminal of the comparator.

Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.

Abstract: A buck voltage converter comprising a high side switch, a low side switch, a capacitor, an inductor, a gate driver circuit having outputs coupled to the gate terminal of the high side switch and the gate terminal of the low side switch, and a separate voltage regulator circuit that powers circuitry internal to the buck voltage converter. The voltage regulator circuit includes a multiplexer having a first multiplexer input coupled to the input voltage source, a second multiplexer input coupled to the buck output of the buck voltage converter, and one or more multiplexer control inputs to select which of the two multiplexer inputs is coupled to a multiplexer output and pass transistor having a first terminal coupled to the multiplexer output of the multiplexer and having a second terminal coupled to the regulator output of the voltage regulator.

Abstract: A bearing system having a housing component, a shaft being supported in the housing component with the aid of a bearing, especially using a roller bearing, wherein the bearing is accommodated in a stepped bore in the housing component, which especially extends through the housing component, a lid part seals the stepped bore, especially with respect to the outside, the lid part is frictionally connected to the housing component, the lid part is accommodated in the stepped bore, a surface section of the outside of the lid part is situated in alignment with a step of the stepped bore, in particular in such a way that the surface section is situated on an axial position of the step.

Abstract: A gate-charge harvester includes a harvest capacitor that has a first plate and a second plate. The second plate is coupled to a lower rail and the first plate is coupled to send a voltage towards a regulator. The gate-charge harvester also includes a low-side harvest transistor having a first terminal coupled to a gate of a low-side power transistor and a second terminal coupled to the first plate.