Abstract: A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

Abstract: A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

Abstract: The invention relates to a method for modulation, augmentation and/or stimulation of neural tissue and/or neural tissue related functionality with stimulating neural tissue and/or neural tissue related functionality with stimuli by which neural activity related local perfusion changes, electro-neuro-chemical, biochemical, neural modulative or neuroplastical responses and/or alterations in ‘metabolism supply lines-neural tissue’ interaction processes in vertebrates can be triggered and/or influenced.

Abstract: A method and an apparatus for determining the particle content of a particle stream using a source of light and two receivers arranged offset from one another in the flow direction of the particle stream. The receivers provide an electrical signal to an evaluation unit as a function of the radiation intensity which they receive, and this signal makes possible a determination of the flow velocity and particle size. Coincident passage of two particles is indicated by a pulse occurring in the signal due to a “roof collapse” in the pulse caused by a weakening of the radiation intensity as the particles pass a receiver.

Abstract: A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n?1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.

Abstract: The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.

Abstract: A memory including an input register, an input pointer circuit, and an output pointer circuit. The input register is configured to receive and latch-in valid and invalid data via an input pointer and to output the valid data via an output pointer. The input pointer circuit is configured to provide the input pointer based on a continuously running write data strobe clock signal. The output pointer circuit is configured to provide the output pointer based on an external clock signal and to update the output pointer to point to the valid data in the input register based on a write signal.

Abstract: A method and apparatus for an integrated circuit with programmable memory cells which are arranged between a first and a second conductor for supplying first and second voltage is provided. A control circuit is arranged between the memory cells and the second conductor. The control circuit controls a change time during which at least one of the memory cells is supplied with a changing current from the second supply changing a state of the memory cell. The control circuit senses the state of the memory cell and stops the erasing current when the memory cell is in a changed state. Furthermore an embodiment refers to a data system with a programmable memory and a method of operating an integrated circuit. Another embodiment refers to a method of operating an integrated circuit.

Abstract: An integrated circuit includes an array of resistivity changing memory cells. The integrated circuit includes a circuit configured to invert a data word to be written to the array in response to determining that writing the inverted data word would use less power than writing the non-inverted data word.

Abstract: The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.

Abstract: An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a temporary data register. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for moving the FIFO output pointer based on data read from the FIFO cells. The temporary data register is for storing a single bit representing one or more bits in each FIFO cell.

Abstract: A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the basis of one or more successive write commands. The second FIFO is clocked by an internal clock signal and stores, for a write operation, only addresses associated with valid write data of the write data stored in the first FIFO.

Abstract: The invention relates to an apparatus for transcutaneous application of a stimulus or for transcutaneous measurement of a parameter on or from the skin surface of a vertebrate, in particular a human. The invention provides, in order to make the nerve stimulation in particular efficient, ergonomically favourable and easily manipulable for the patient, that the apparatus is designed so that it can be accommodated completely in the pinna (external ear) of the vertebrate.

Abstract: A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer. The reference signal comprises an information regarding a read latency to be adjusted utilizing the output pointer, the at least one counter provides an m-bit counter reading signal comprising a current counter reading, and the decoder arrangement comprises a plurality of decoder devices each comparing the current counter reading signal with a reference value which is associated with a respective of the decoder devices. Each decoder device provides one bit of the output pointer on the basis of the comparing.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.

Abstract: An integrated circuit having a resistive memory including a resistive memory element, a selection device, a conductive line, and a reference electrode is disclosed. In one embodiment, the conductive line is set to a first voltage for establishing a first resistive state of the resistive memory element and to a second voltage, being lower than the first voltage, for establishing a second resistive state of the resistive memory element. The reference electrode is coupled to the resistive memory element and is set to a voltage level being provided between the first voltage and the second voltage.

Abstract: An electric circuit for inverting a data bit of a data burst read out from a memory module comprises a buffer for buffering a data burst being comprised of at least two data words, a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously two neighbouring data words of the data words buffered in the buffer and generating an inversion flag, if the number of different data bits of the two neighbouring data words exceeds half the number of data bits of a data word, a correction device for generating a corrected inversion flag for a specific decoder of the decoders by inverting or not inverting the inversion flag of the specific decoder dependent on the inversion flag generated by the specific decoder and the inversion flags generated by the remaining of the decoders, and an inversion device comprised of a plurality of inverters, each inverting or not inverting a present of the data words of an associated of the decoders dependent on the corrected inversion

Abstract: The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.