Abstract: A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level and an interconnection level having vias includes providing the first level and a dielectric layer, randomly depositing particles on the dielectric layer, depositing an etching mask on the dielectric layer and the particles, and planarizing, so as to obtain a composite layer including the particles. The method also includes forming a lithographic layer having opening patterns, etching the composite layer through the opening patterns to form mask openings, then etching the dielectric layer through the mask openings, so as to obtain functional via openings and degraded via openings, and filling the via openings so as to form the vias of the interconnection level, said vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

Abstract: A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level and an interconnection level including vias, includes providing the first level and a dielectric layer, forming an etching mask on the dielectric layer, randomly depositing particles on the etching mask, and forming a lithographic layer having opening patterns. The mask layer is etched through opening patterns to form mask openings, then the dielectric layer is etched through the mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

Abstract: A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level, and an interconnection level comprising vias, includes providing the first level and a dielectric layer, forming an etching mask having openings on the dielectric layer, and randomly depositing particles in the openings, by deposition then recirculating the particles on the surface of the etching mask. The dielectric layer is etched through mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

Abstract: The invention is based on a method for producing an individualisation zone of a chip comprising a component level and a contact level comprising vias, the method comprising the following steps: providing the components level and a dielectric layer, forming a mask on the dielectric layer, etching the dielectric layer through mask openings so as to form openings opening onto the contact zones of the components level, forming fluorinated residue by inputting fluorinated species on at least some contact zones, the openings thus comprising openings with fluorinated residue and openings without residue, filling the openings so as to form the vias of the contact level, said vias comprising functional vias at the openings without residue and altered vias at the openings with residue.

Abstract: A multispectral filter matrix for an electromagnetic wave, the matrix including at least a first and a second optoelectronic element, each optoelectronic element including a colour filter and a photoelectric transducer facing the filter, each colour filter forming a Fabry-Perot cavity including a first reflective layer, a second reflective layer and a Fabry-Perot cavity layer of dielectric material between the first reflective layer and the second reflective layer, the layer of dielectric material including a lower surface, in contact with the first reflective layer; the lower surface being curved, an upper surface in contact with the second reflective layer, the upper surface being curved, the average thicknesses of the two layers of dielectric material of the two filters being different.

Abstract: A method for manufacturing a multispectral filter for electromagnetic radiation including two colour filters each including a first reflective layer, a second reflective layer, a layer of dielectric material of Fabry-Perot cavity, the thickness of the dielectric layer of both colour filters being different and each of both filters facing a photoelectric transducer. The method includes depositing a resin layer onto a handle substrate, structuring the resin layer to obtain two resin patterns of different heights, at least one of the patterns having a maximum reference height; depositing a dielectric layer to form the dielectric patterns of the Fabry-Perot cavities and planarising; transferring the planarised face of the handle substrate to the upper face of a carrier substrate; removing the handle substrate and the resin and depositing a reflective layer onto the at least two dielectric patterns of Fabry-Perot cavity, forming the second reflective layer.

Abstract: A method for producing an individualisation zone of a chip including a first and a second level of electric tracks, and an interconnecting level including vias, the method including the following steps: providing the first level and a dielectric layer with the basis of a dielectric material including a non-zero nitrogen concentration, forming a mask on the dielectric layer, etching the dielectric layer through mask openings by a vapour HF etching, so as to form: openings leading to the first level of electric tracks, nitrogenous residues randomly distributed at the level of certain openings, the openings thus including openings with nitrogenous residues and openings without residues, filling the openings so as to form the vias of the interconnecting level, the vias including functional vias at the level of openings without residues and inactive vias at the level of the openings with residues.

Abstract: A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.

Abstract: A method for making at least one structure having sidewalls with different inclinations includes providing a stack including a substrate having a layer of a positive resin whose tone could be reversed when exposed to an insolation dose D<Dinversion, the patterns exposed to the dose Dinversion not being sensitive to creeping at the glass-transition temperature Tfluage of the resin; forming a non-sensitive first pattern by exposing the resin to a first dose D1?Dinversion, the first pattern having a first sidewall having a first inclination; and forming a creep-sensitive second pattern by exposing the resin to a second dose D2<Dinversion. Creeping is performed by applying a temperature T?Tfluage to make the second pattern creep over a portion of the first pattern by leaving uncovered at least partially the first sidewall of the first pattern, and defining at least one second sidewall having a second inclination different from the first inclination.

Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.

Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.

Abstract: A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.

Abstract: A method for functionalising a substrate intended for the self-assembly of a block copolymer, includes depositing on the surface of a substrate a layer of a first polymer material, the first polymer having a first chemical affinity with respect to the block copolymer; grafting one part only of the first polymer material layer onto the surface of the substrate; printing, using a mould, patterns in a sacrificial layer arranged above the grafted part of the first polymer material layer; transferring the patterns of the sacrificial layer into the grafted part of the first polymer material layer, until the substrate is reached; and removing at least one part of the sacrificial layer by wet etching, so as to uncover the grafted part of the first polymer material layer.

Abstract: A method for producing a structure having at least one curved pattern includes providing a substrate having a front face, where one portion is structured by at least one plurality of reliefs, the reliefs of each plurality defining spaces therebetween, and another portion is free of reliefs. The method also includes depositing a base layer of a material such as a polymer or a glass, on the front face of the substrate, at least in line with the reliefs, and allowing the material of the base layer to at least partially fill the at least one of the spaces by deformation. The base layer is thus deformed so that its free surface has at least one curved pattern.

Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a conductor layer (30A) comprising via holes (30), the method comprising the following steps: providing at least one dielectric layer (200, 201, 202) having a thickness hd, forming a metal mask layer (300) having a thickness hm and a residual stress ?r on the at least one dielectric layer (200, 201, 202), etching the layer (300) so as to form line patterns (310) of width l, etching the at least one dielectric layer (200, 201, 202) between the line patterns (310) so as to form trenches (210) separated by walls (211), filling the trenches (210) with an electrically conductive material so as to form the electrical tracks (10, 10KO) of the first level (10A), forming via holes (30, 30OK, 30KO1, 30KO2) of the conductor layer (30A), forming the second level (20A) of electrical tracks (20, 20OK), the method being characterized in that the thickn

Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a level of interconnections (30A) comprising vias (30), the method comprising the following steps: providing the first level (10A) and a dielectric layer (200, 201, 202), making a hard metal mask (300) on the dielectric layer (200, 201, 202), etching the dielectric layer (200, 201, 202) through the mask openings (301) by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask (300) by hydrolysis so as to form randomly distributed residues (31) at certain openings (320R), filling the openings (320, 320R) so as to form at least the vias (30) of the level of interconnections (30A), said vias (30) comprising functional vias (30OK) at the openings without residues (320) and inactive vias (30KO) at the openings with residues (320R).

Abstract: A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.

Abstract: A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.

Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.

Abstract: A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity ?1 less than a resistivity ?2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.