Abstract: In an embodiment, a transistor device is provided that includes a semiconductor substrate having a first major surface, and a columnar trench arranged in the first major surface and having a lower surface and a side wall, the side wall extending from the lower surface to the first major surface. A gate electrode positioned in the columnar trench is electrically insulated from the semiconductor substrate by a gate dielectric. A field plate positioned in the columnar trench under the gate electrode is electrically insulated from the gate electrode and the semiconductor substrate by a field dielectric. The gate electrode is asymmetric about a longitudinal axis of the columnar trench. The field plate includes a field plate extension which extends from the field plate towards the first major surface and laterally adjacent to the gate electrode.

Abstract: In an embodiment, a transistor device includes a semiconductor substrate having at least one transistor cell. The transistor cell includes an elongate trench and an elongate mesa. The elongate trench is arranged in the first major surface of the semiconductor substrate and includes an elongate gate electrode electrically separated from the semiconductor substrate by a gate dielectric. A first insulating layer arranged on the first major surface covers the elongate trench. An elongate contact connection strip arranged on the first insulating layer extends above and parallel to the elongate trench. The elongate contact connection strip is electrically connected to the elongate gate electrode in the elongate trench by at least one first contact that extends through the first insulating layer.

Abstract: The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Abstract: In an embodiment, a power transistor device includes a substrate formed of crystalline silicon and having a first surface and a second surface opposing the first surface. A field plate formed of polysilicon is electrically connected with the substrate. An interfacial silicon nitride layer is arranged between the polysilicon of the field plate and the crystalline silicon of the substrate.

Abstract: The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field including transistor cells, and an edge termination region laterally surrounding the cell field. Each transistor cell includes a drift region of a first conductivity type, a first body region of a second conductivity type on the drift region, a source region of the first conductivity type on the first body region and a gate electrode. The transistor device further includes an elongate source contact having opposing first and second distal ends, the elongate source contact being in contact with the source region, and a second body region of the second conductivity type positioned in the semiconductor substrate. The second body region has a lateral extent such that it is spaced part from the second distal end of the elongate source contact and extends laterally beyond the first distal end of the elongate source contact.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field, and an edge termination region laterally surrounding the cell field. The cell field includes elongate trenches that extend from the first major surface into the semiconductor substrate and that are positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches and elongate mesas, each elongate mesa being formed between neighbouring elongate trenches. The elongate mesas include a drift region, a body region on the drift region and a source region on the body region. In a top view, one or both of the outermost elongate trenches has a different contour from the one or more inner elongate trenches.

Abstract: In an embodiment, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap and first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etch process, selectively removing a portion of the first conductive material using a second etch process, and forming a field plate in a lower portion of the elongate active trench and selectively removing a second portion of the first insulating material using a third etch process. The first etch process is carried out before the second etch process and the second etch process is carried out before the third etch process.

Abstract: The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Abstract: The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input the drive circuit region arranged closer to the inner region than the level shifter region.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, the drive circuit region arranged closer to the inner region than the level shifter region.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, the drive circuit region arranged closer to the inner region than the level shifter region.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; and a first drive circuit integrated in a first drive circuit region of the semiconductor body. The first drive circuit is configured to be connected to a level shifter and to drive a second transistor device. The first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.

Abstract: In an embodiment, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap and first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etch process, selectively removing a portion of the first conductive material using a second etch process, and forming a field plate in a lower portion of the elongate active trench and selectively removing a second portion of the first insulating material using a third etch process. The first etch process is carried out before the second etch process and the second etch process is carried out before the third etch process.

Abstract: A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.