Abstract: A semiconductor device includes a first ridge and a second ridge extending from a first main surface of a semiconductor substrate. The first and second ridges run in a first direction. The semiconductor device further includes a body region disposed in a portion of the semiconductor substrate between the first ridge and the second ridge, and a gate electrode adjacent to the body region. The first and second ridges are connected with the body region. A plurality of further ridges are formed in the body region, the further ridges extending in a second direction intersecting the first direction. The gate electrode runs in the first direction, and the gate electrode is disposed at at least two sides of the further ridges.

Abstract: A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

Abstract: An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

Abstract: A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width.

Abstract: A method for manufacturing an integrated circuit may include forming an electronic circuit in or above a carrier; forming at least one metallization layer structure configured to electrically connect the electronic circuit; and forming a solid state electrolyte battery at least partially in the at least one metallization layer structure, wherein the solid state electrolyte battery is electrically connected to the electronic circuit.

Abstract: A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion. A channel/body zone is formed in a transistor fin that extends between the first and second electrode fins at a distance to the first surface. The first and second electrode fins extend along a first lateral direction. A width of first gate sections, which are arranged on opposing sides of the transistor fin, along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins.

Abstract: A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.

Abstract: An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality of microstructures define a detectable first state if they are not bent such that end portions thereof, which are distal with respect to the support, do not touch each other, and the two adjacent microstructures of the plurality of microstructures define a detectable second state if they are bent such that the end portions thereof, which are distal with respect to the support, touch each other and are fixed to each other.

Abstract: A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure.

Abstract: According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier, and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier.

Abstract: According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

Abstract: A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.

Abstract: A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner.

Abstract: A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width.

Abstract: A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.

Abstract: A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner.

Abstract: A semiconductor device includes a first ridge and a second ridge extending from a first main surface of a semiconductor substrate. The first and second ridges run in a first direction. The semiconductor device further includes a body region disposed in a portion of the semiconductor substrate between the first ridge and the second ridge, and a gate electrode adjacent to the body region. The first and second ridges are connected with the body region. A plurality of further ridges are formed in the body region, the further ridges extending in a second direction intersecting the first direction. The gate electrode runs in the first direction, and the gate electrode is disposed at at least two sides of the further ridges.

Abstract: A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.

Abstract: A method for manufacturing an integrated circuit may include forming an electronic circuit in or above a carrier; forming at least one metallization layer structure configured to electrically connect the electronic circuit; and forming a solid state electrolyte battery at least partially in the at least one metallization layer structure, wherein the solid state electrolyte battery is electrically connected to the electronic circuit.

Abstract: An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.