Patents by Inventor Steffen Sonnekalb
Steffen Sonnekalb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12079507Abstract: A storage device comprises a plurality of bitwise-modifiable memory cells. A control device is also provided, which, in order to modify existing data content written to a group of memory cells with new data content to be written, is designed to compare the existing data content and the data content to be written in order to obtain a comparison result. The control device is designed to determine a subset of the group of memory cells for modification and a remaining length based on the comparison result, and to write the data content to be written to the subset, leaving the remaining set at least partially unchanged. For modifying the existing data content, the storage device is designed to read from a memory location of the storage device and to verify the correctness of the memory location.Type: GrantFiled: February 8, 2022Date of Patent: September 3, 2024Assignee: Infineon Technologies AGInventor: Steffen Sonnekalb
-
Patent number: 12038808Abstract: A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.Type: GrantFiled: April 24, 2023Date of Patent: July 16, 2024Assignee: Infineon Technologies AGInventor: Steffen Sonnekalb
-
Publication number: 20230367912Abstract: A semiconductor chip apparatus including a memory having a plurality of memory locations, a memory access element, and an integrity check device configured to store a reference value for a check function over values stored in the memory locations and, in a case of write access to a memory location, configured to update a check value with the value to be written by the write access if the check value represents the value stored in the memory location prior to the write access, and configured to compare the reference value with the check value after the check value has been generated and output a signal depending on a result of the comparison.Type: ApplicationFiled: May 4, 2023Publication date: November 16, 2023Inventors: Marcus Janke, Steffen Sonnekalb
-
Publication number: 20230359523Abstract: A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.Type: ApplicationFiled: April 24, 2023Publication date: November 9, 2023Inventor: Steffen Sonnekalb
-
Publication number: 20220261176Abstract: A storage device comprises a plurality of bitwise-modifiable memory cells. A control device is also provided, which, in order to modify existing data content written to a group of memory cells with new data content to be written, is designed to compare the existing data content and the data content to be written in order to obtain a comparison result. The control device is designed to determine a subset of the group of memory cells for modification and a remaining length based on the comparison result, and to write the data content to be written to the subset, leaving the remaining set at least partially unchanged. For modifying the existing data content, the storage device is designed to read from a memory location of the storage device and to verify the correctness of the memory location.Type: ApplicationFiled: February 8, 2022Publication date: August 18, 2022Inventor: Steffen Sonnekalb
-
Publication number: 20220253231Abstract: Processing of data stored in a memory, wherein the data are deleted depending on a functional setting if an operation is performed on the data.Type: ApplicationFiled: January 18, 2022Publication date: August 11, 2022Inventors: Erich Wenger, Steffen Sonnekalb
-
Patent number: 11086796Abstract: A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.Type: GrantFiled: May 24, 2019Date of Patent: August 10, 2021Assignee: Infineon Technologies AGInventors: Berndt Gammel, Gerd Dirscherl, Bernd Meyer, Steffen Sonnekalb
-
Patent number: 11010296Abstract: A memory arrangement having a memory, a first buffer memory, a first buffer memory controller which, during the storage of memory contents from the memory in the first buffer memory, is configured to invalidate the memory contents in the memory by means of a modification, a second buffer memory and a second buffer memory controller which is configured to read memory contents from the memory, to check whether the memory contents read from the memory are valid and, if the memory contents read from the memory are invalid, to apply a reversal of the modification to the read memory contents.Type: GrantFiled: October 23, 2018Date of Patent: May 18, 2021Assignee: Infineon Technologies AGInventor: Steffen Sonnekalb
-
Patent number: 10937469Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.Type: GrantFiled: October 29, 2019Date of Patent: March 2, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb
-
Patent number: 10867028Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.Type: GrantFiled: November 8, 2019Date of Patent: December 15, 2020Assignee: Infineon Technologies AGInventors: Berndt Gammel, Stefan Mangard, Steffen Sonnekalb
-
Patent number: 10785031Abstract: A method for encrypting data stored in a memory area is proposed, wherein the data are encrypted on the basis of a key identification for the data and on the basis of a one-time key.Type: GrantFiled: January 23, 2015Date of Patent: September 22, 2020Assignee: Infineon Technologies AGInventor: Steffen Sonnekalb
-
Patent number: 10649931Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.Type: GrantFiled: January 28, 2019Date of Patent: May 12, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Gerd Dirscherl, Benedikt Driessen, Gunther Fenzl, Franz Klug, Bernd Meyer, Steffen Sonnekalb
-
Patent number: 10628084Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.Type: GrantFiled: October 10, 2018Date of Patent: April 21, 2020Assignee: Infineon Technologies AGInventors: Joel Hatsch, Bernd Meyer, Jan Otterstedt, Steffen Sonnekalb
-
Publication number: 20200074076Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Inventors: Berndt Gammel, Stefan Mangard, Steffen Sonnekalb
-
Publication number: 20200066312Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.Type: ApplicationFiled: October 29, 2019Publication date: February 27, 2020Inventors: Jan OTTERSTEDT, Robin BOCH, Gerd DIRSCHERL, Bernd MEYER, Christian PETERS, Steffen SONNEKALB
-
Patent number: 10515206Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.Type: GrantFiled: March 1, 2012Date of Patent: December 24, 2019Assignee: Infineon Technologies AGInventors: Berndt Gammel, Stefan Mangard, Steffen Sonnekalb
-
Patent number: 10514892Abstract: An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.Type: GrantFiled: July 26, 2013Date of Patent: December 24, 2019Assignee: Infineon Technologies AGInventors: Berndt Gammel, Stefan Mangard, Steffen Sonnekalb
-
Publication number: 20190370190Abstract: A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.Type: ApplicationFiled: May 24, 2019Publication date: December 5, 2019Inventors: Berndt Gammel, Gerd Dirscherl, Bernd Meyer, Steffen Sonnekalb
-
Patent number: 10497408Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb
-
Patent number: 10475520Abstract: A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.Type: GrantFiled: November 24, 2017Date of Patent: November 12, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb