Abstract: An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the 1-out-of-n decoder, and a comparer for receiving the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.

Abstract: An error detection device for a command decoder is described, the command decoder reading out an associated sequence of control signal words from a command memory based on an input word, wherein the sequence of control signal words has at least one control signal word, having: a controller designed to provide the input word at a first time and the input word at a second time for reading out the command memory, wherein the second time is delayed with respect to the first time, to effect a readout of the sequence of control signal words at a first time and a readout of the sequence of control signal words at a second time; and a comparator designed to receive and compare the associated sequences of control signal words read out at the first and second times, and to output a signal indicating an error if the associated sequences of control signal words read out at the first and second times are different.

Abstract: An encryption part or a decryption part of an encryption/decryption apparatus or a part common to both parts is used both for encryption and decryption of a datum to be stored and the encrypted memory content and for the generation of the address-individual key and the address-dependent key, respectively.

Abstract: A device for reading out a predetermined data word from a memory in which a data block is divided into a plurality of data words including the predetermined data word, an error identification value associated with the respective data word per data word of the plurality of data words, and a correction value associated with the data block are stored, having an error identifier implemented to check whether the predetermined data word comprises a predetermined relation to the associated error identification value to conclude that there is an error if the predetermined relation is not present, and an error corrector implemented to correct, if the predetermined data word does not have the predetermined relation to the associated error identification value, the error using the correction value, wherein the error corrector is implemented to use the correction value independent of which data word of the plurality of data words is the predetermined data word.

Abstract: A memory arrangement having a memory area with a plurality of memory locations, to which external addresses can be allocated, and an address decoder which is coupled to the memory area and which includes an address input for applying an external address. The address decoder can be switched so that one of the external addresses of an address range is allocated to each memory location of the memory area, or that one of the external addresses of a sub-address range of the address range is allocated to each memory location only within a part-memory area of the memory area. The address decoder is also arranged for identifying the memory location allocated to the external address applied.

Abstract: An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present to determine whether they have a predefined relationship with predefined values, and to output data indicating the test result at the output. The testing unit is also designed to start the functional self test by internal circuit means and to evaluate the test results present.

Abstract: The method comprises providing a part-data record to be changed from a data record stored in a memory device, providing a change data record changing the part-data record to be changed and providing a check word associated with the data record. The check word is changed by a change transformation in dependence on the part-data record to be changed, the changing change data record and the check word provided. Furthermore, the method comprises performing the data record change in the memory device in dependence on the change data record and associating the changed check word with the changed data record. The changed data record is transformed into a further check word.

Abstract: An undesired change of encrypted data words of a stored encrypted dataset may be concluded from the fact that redundancy information is associated with the data words of a dataset prior to encryption, wherein the redundancy information is also encrypted and stored at least partially together with the encrypted data words of the encrypted dataset as an encrypted redundancy data word. The change of the stored encrypted data words may be concluded from the fact that the decrypted data words resulting from decrypting the encrypted data words are used to form a new redundancy data word which is encrypted into a new encrypted redundancy data word. A comparison of the new encrypted redundancy data word to the encrypted redundancy data word enables to examine whether the encrypted data was changed.

Abstract: An encryption unit and decryption unit located in an encryption/decryption device may be used both for encryption and decryption, without their effects canceling each other out when, between the decryption input of the decrypter and the encryption output of the encrypter. An encryption combiner maps the encryption result data block at the encryption output to a mapped encryption result data block according to an encryption combining mapping and is exemplarily used when encrypting. A decryption combiner maps the encryption result data block at the encryption output to an inversely mapped encryption result data block according to a decryption combining mapping which is inverse to the encryption combining mapping and is exemplarily used when decrypting.

Abstract: Apparatus and method for generating an individual key for accessing a predetermined addressable unit of a memory divided into addressable units. The apparatus includes a calculator for calculating a page pre-key based on a page address, a determiner for determining the individual key based on the page pre-key and a unit address, a memory for storing the calculated page pre-key, and a checker for checking whether during a next access to a further predetermined unit to which a further unique address is associated, an already calculated page pre-key exists in a temporary memory, which has been calculated based on a page address of a unique address, which is identical to the page address of the further unique address, and, if so, transmitting the already calculated page pre-key to the determiner by bypassing the calculator, and, if not, transmitting the page address of the further unique address to the calculator.

Abstract: Applying both an encryption and also a decryption algorithm, which is inverse to the encryption algorithm, as an encryption definition to thereby enable the use of an encryption unit and a decryption unit of an encryption/decryption device simultaneously, i.e. temporally overlapping, in an encryption process when a part of the data to be encrypted is supplied to the encryption unit while the other part is supplied to the decryption unit. The result is encrypted data or is a cipher text, respectively, whose parts are only “encrypted” in a different way. During decryption, it only has to be guaranteed by suitable regulations that those parts which were encrypted by the encrypted unit are again decrypted by the decryption unit, while the other parts which were “encrypted” by the decryption unit are “decrypted” by the encryption unit.

Abstract: Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

Abstract: A method and an apparatus for reading instruction codes and for forwarding the corresponding instructions to the instruction unit that are distinguished, in particular, by buffer-storing the instructions of program loops that do not exceed the storage capacity of the instruction FIFO, in full, in the instruction FIFO. During a “loop mode”, such program loops are then executed only from the instruction FIFO itself and the instructions do not need to be repeatedly reloaded from the memory. This loop mode is then maintained until the jump instruction at the end of the program loop finally refers to an instruction other than that at the start of the loop.

Abstract: A method for verifying a data record having a plurality of data words, the method including the steps of providing an encrypted data record having a plurality of encrypted data words and an error codeword assigned to the data record. After the decryption of the encrypted data words, it is verified whether the error codeword is to be assigned to the decrypted data words. If the error codeword is not to be assigned, an alarm action is performed.

Abstract: A program-controlled unit stores return addresses not only in a system stack but also in a return stack. The instructions which have already been taken into the program-controlled unit, but are not currently required, are stored in a storage device for alternative instructions. At times when the program-controlled unit is not active elsewhere, instructions are taken into the program-controlled unit, whereby the instructions are to be carried out when an instruction is not carried out or is not carried out as expected.

Abstract: A method for operating a microprocessor in which there is at least one program branch and/or program delay which is implemented under random-bit control and as a hardware-based command in order to modulate a program flow and which ensures that every pass through a particular program brings about a respective program execution time which is different than that in preceding program passes.

Abstract: A controller has a receiver for receiving an instruction, the instruction being an executable instruction or a wildcard instruction. A decoder is formed to output a control signal corresponding to the executable instruction responsive to an executable instruction, and to output a switch signal responsive to a received wildcard instruction. Additionally, the controller has a provider for providing a predetermined substitute control signal outputting the predetermined substitute control signal depending on the switch signal.

Abstract: A controller having a receiver for receiving an instruction, a comparator for comparing the received instruction to a predetermined wildcard instruction, the comparator providing a switch signal to a provider for providing a predetermined substitution instruction responsive to the predetermined wildcard instruction. Depending on the switch signal, the provider outputs the received instruction or the other instruction.

Abstract: Device for determining a result includes a unit for determining a first and a second intermediate result, wherein the result depends on the first and the second intermediate result, and a unit for randomly determining a sequence in which the unit for determining executes the determination of the first and the second intermediate result.

Abstract: Circuit having a bus, a first receiver circuit part coupled to the bus for processing a signal on the bus, a second receiver circuit part coupled to the bus for processing a signal on the bus, a transmitter circuit part coupled to the bus for output-ting a signal on the bus, and a unit for preventing processing a signal on the bus by the first receiver circuit part in response to a control signal.