Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

Abstract: A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.

Abstract: A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode.

Abstract: In various embodiments, a memory circuit is provided. The memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, wherein each word portion is configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion comprising a plurality of overlay memory cells, wherein each of the plurality of overlay portions comprises an overlay word, wherein the memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, thereby providing, as an output of the read operation, a result of a logic operation performed on the data word and the overlay word.

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

Abstract: A chip is provided having processing circuits, each processing circuit configured to process a data vector to be stored according to a multiplication of the vector by a processing matrix, the sum of the processing matrices corresponding to the non-unit-matrix part of a generator matrix of a predetermined linear code in reduced form, a summing circuit to sum the results of the processing operations of the data vector, a storage circuit to store the data vector to be stored together with the sum of the generated results as one data word in a memory, a read-out circuit to read the stored data word out of the memory, and a decoding circuit to check whether the data word read out is a valid code word of the linear code and to output an error signal if the data word is not a valid code word of the linear code.

Abstract: A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode.

Abstract: A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.

Abstract: A method for encrypting data stored in a memory area is proposed, wherein the data are encrypted on the basis of a key identification for the data and on the basis of a one-time key.

Abstract: An apparatus includes a pair of an alarm condition generator and an associated alarm circuit and a test circuit. The alarm circuit is configured to generate an alarm signal in response to a detection of an associated alarm condition. The alarm condition generator is configured to generate the associated alarm condition for its associated alarm circuit in response to a reception of a first reset of a first type of reset. The test circuit is configured to receive the alarm signal and the first reset and to generate in response to a reception of both the first reset and the alarm signal a second reset of a second type of reset.

Abstract: An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.

Abstract: An apparatus includes a pair of an alarm condition generator and an associated alarm circuit and a test circuit. The alarm circuit is configured to generate an alarm signal in response to a detection of an associated alarm condition. The alarm condition generator is configured to generate the associated alarm condition for its associated alarm circuit in response to a reception of a first reset of a first type of reset. The test circuit is configured to receive the alarm signal and the first reset and to generate in response to a reception of both the first reset and the alarm signal a second reset of a second type of reset.

Abstract: A memory device includes a first memory portion and a second memory portion. The second memory portion includes a security functionality. The size of the first memory portion and the size of the second memory portion are adjustable.

Abstract: A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.

Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Abstract: An encryption part or a decryption part of an encryption/decryption apparatus or a part common to both parts is used both for encryption and decryption of a datum to be stored and the encrypted memory content and for the generation of the address-individual key and the address-dependent key, respectively.

Abstract: A device for reading out a predetermined data word from a memory in which a data block is divided into a plurality of data words including the predetermined data word, an error identification value associated with the respective data word per data word of the plurality of data words, and a correction value associated with the data block are stored, having an error identifier implemented to check whether the predetermined data word comprises a predetermined relation to the associated error identification value to conclude that there is an error if the predetermined relation is not present, and an error corrector implemented to correct, if the predetermined data word does not have the predetermined relation to the associated error identification value, the error using the correction value, wherein the error corrector is implemented to use the correction value independent of which data word of the plurality of data words is the predetermined data word.

Abstract: Apparatus and method for generating an individual key for accessing a predetermined addressable unit of a memory divided into addressable units. The apparatus includes a calculator for calculating a page pre-key based on a page address, a determiner for determining the individual key based on the page pre-key and a unit address, a memory for storing the calculated page pre-key, and a checker for checking whether during a next access to a further predetermined unit to which a further unique address is associated, an already calculated page pre-key exists in a temporary memory, which has been calculated based on a page address of a unique address, which is identical to the page address of the further unique address, and, if so, transmitting the already calculated page pre-key to the determiner by bypassing the calculator, and, if not, transmitting the page address of the further unique address to the calculator.

Abstract: A method for the protected transmission of data words involves provision of a first data word (X1), transformation of the first data word (X1) into a sequence comprising at least one second data word (X2) by a first transformation rule (T1), transformation of at least one of the second data words (X2) into a third data word (X3) by a second transformation rule (T2), and checking whether a prescribed relationship exists between the third data word (X3) and a comparison data word (VX).

Abstract: Method for protected transmission of data words includes providing a first data word, transforming the first data word into a sequence including at least one second data word using a first transformation rule, transforming at least one of the second data words into a third data word using a second transformation rule, and checking whether a prescribed relationship exists between the third data word and a comparison data word.