Patents by Inventor Stephen Daley Arthur

Stephen Daley Arthur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735263
    Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 15, 2017
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Almern Losee, Alexander Viktorovich Bolotnikov
  • Patent number: 9576868
    Abstract: A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 21, 2017
    Assignee: General Electric Company
    Inventors: Joseph Darryl Michael, Stephen Daley Arthur
  • Publication number: 20160307997
    Abstract: A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Motocha, Richard Joseph Saia, Zachary Matthew Stum, Ljuibisa Dragolijub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Patent number: 9406762
    Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: August 2, 2016
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Patent number: 9379189
    Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: June 28, 2016
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Michah Sandvik, Stephen Daley Arthur
  • Publication number: 20160087091
    Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 24, 2016
    Inventors: Stephen Daley Arthur, Kevin Sean MATOCHA, Ramakrishna RAO, Peter Almern LOSEE, Alexander Viktorovich BOLOTNIKOV
  • Patent number: 9257283
    Abstract: A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 9, 2016
    Assignee: General Electric Company
    Inventors: Joseph Darryl Michael, Stephen Daley Arthur, Tammy Lynn Johnson, David Alan Lilienfeld
  • Patent number: 9123798
    Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 1, 2015
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Losee, Alexander Viktorovich Bolotnikov
  • Publication number: 20150236151
    Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: James Jay McMahon, Ljubisa Dragoljub Stevanovic, Stephen Daley Arthur, Thomas Bert Gorczyca, Richard Alfred Beaupre, Zachary Matthew Stum, Alexander Viktorovich Bolotnikov
  • Publication number: 20150187884
    Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.
    Type: Application
    Filed: March 11, 2015
    Publication date: July 2, 2015
    Inventors: Avinash SRIKRISHNAN KASHYAP, Peter Michah SANDVIK, Stephen Daley ARTHUR
  • Publication number: 20150144960
    Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: General Electric Company
    Inventors: Richard Joseph Saia, Stephen Daley Arthur, Zachary Matthew Stum, Roger Raymond Kovalec, Gregory Keith Dudoff
  • Publication number: 20150115284
    Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
    Type: Application
    Filed: May 15, 2013
    Publication date: April 30, 2015
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Patent number: 9006027
    Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Ahmed Elasser, Stephen Daley Arthur, Stanislav I. Soloviev, Peter Almern Losee
  • Patent number: 8987858
    Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 24, 2015
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
  • Publication number: 20140361315
    Abstract: A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 11, 2014
    Inventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee
  • Publication number: 20140264775
    Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
  • Patent number: 8815721
    Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 26, 2014
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee
  • Patent number: 8765524
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: July 1, 2014
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Publication number: 20140159141
    Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Losee, Alexander Viktorovich Bolotnikov
  • Patent number: 8691634
    Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: April 8, 2014
    Assignee: General Electric Company
    Inventors: Ahmed Elasser, Stephen Daley Arthur, Alexey Vert, Stanislav Ivanovich Soloviev, Peter Almern Losee